1BR 6/00 1ECE/CS 3724 - Microprocessors• Everything relating to the class is posted on:http://www.ece.msstate.edu/~reese/EE3724• Most of the course lecture notes are linked to WWW page -- print them out before class and bring them to lecture• Be sure to read the class Policy/Syllabus, and follow the link to the EE 3724 LAB page• Lots of material in this class - don’t fall behind!BR 6/00 2Approaches to Digital System Design• In Digital Devices, you learned how to create a logic network (Flip-flops + combinational gates) to solve a problem– The logic network was SPECIFIC to the problem. To solve a different problem, needed a different logic network• Another approach is to design a logic network that can used to solve many different problems– This general purpose logic network might not be as efficient (speed, cost) as a special purpose logic network, but hopefully can be used to solve multiple problems!BR 6/00 3A Computer!!• A Computer is a digital system whose operation can be specified via a Program .– Changing the program changes the computer behavior! (solves a different problem!!!).• A Program is simply a sequence of binary codes that represent instructions for the computer. The Program is stored in a Memory . • External inputs to the Computer can also alter the behavior the computer. The computer will have Outputs that can be set/reset via program instructions. – These external inputs/output are know as the I/O section of the computer.2BR 6/00 4Components of any Computer System• Control – logic that controls fetching/execution of instructions• Memory – area where instructions/data are stored• Input/Output – external interaction with computerControlMemoryAddress busDatabus busInput/OutputdevicesBR 6/00 5Problem DefinitionBuild a Digital System based upon your Social Security number (SSN). The Digital System will have one external input called ODD. If ODD is true, then the system will reset to display the LEFTMOST odd digit in your SSN, and then the output will sequence over the odd digits in your SSN, skipping over the even digits.If ODD is false, then the system will reset to display the LEFTMOST even digit in your SSN, and then the output will sequence over the even digits in your SSN, skipping over the odd digits.BR 6/00 6Two Approaches for Solving this ProblemFinite State MachineWill only work for one SSN sequenceCombinationalLogicCircuitMemory Elementnmk kk-bitPresent StateValuek-bitNext StateValueInputs OutputsControlMemoryAddress busDatabus busInput/OutputdevicesComputer SystemWill only work for any SSN sequence, change program to change sequence3BR 6/00 7ASM chart for 458 70 2198odd?0 1Dout = 4 Dout = 5S0Dout = 8 Dout = 0 Dout = 2 Dout = 8 Dout = 7 Dout = 1 Dout = 9 S1S2S3S4S5S6S7Odd only affects sequence in State S0 (Reset state)BR 6/00 8FSM ImplementationUse 3 D-FFs for the 8 states.Use Binary State Encoding: S0=000, S1=001, S2=010, etc… S7 = 111CombinationalLogicCircuitDffsSsn[3:0]333-bitPresent StateValue3-bitNext StateValueOdd OutputsDQClkAlcrRLogic designed fora particular SSN sequence.BR 6/00 9Computer System ImplementationWhat do We Need?Input/Output First4ssn[3:0]Oddssn[3:0] - 4 bit output bus that has the value of the ssn digitodd – 1 bit input that controls whether or not even or odd sequence is displayed4BR 6/00 10Register for holding SSN output value4ssn[3:0]DIN4ldREGaclrOddRegister loads DIN on rising clock edge when ld = 1.Aclr is an asynchronous clear.BR 6/00 11Memory for holding instructions4ssn[3:0]DIN4ldREGaclrOddMEMData[?:0]Address[?:0]Memory is KxN (K locations, each location N bits wide).Don’t know values of K, N yet.BR 6/00 12Register for specifying address – Use counter4ssn[3:0]Din[3:0]4ldREGaclrOddMEMData[?:0]Addr[?:0]?ldcntrenaclrCounter increments on rising clock edge when en = 1.Loads on rising clock edge when ld = 1. Aclr is an asynchronous clear.Din[?:0]5BR 6/00 13What Instructions do we need?Start:If (Odd = 1) goto Odd_startEven_start:output even digit #1output even digit #2……output last even digitgoto StartOdd_start:output odd digit #1output odd digit #2…..output last odd digitgoto StartPsuedo Code foroperationsBR 6/00 14Needed Instructions1. Jc location Jump conditionallyIf odd = 1, then jump to location (counter set equal to specified location). If odd = 0, then fetch next instruction (counter increments by 1).2. Jmp location Jump unconditionalFetch next instruction from location (counter loaded with specified location).3. out dataload output register with data. Used for setting the ssn[3:0] value.BR 6/00 15Instruction Encoding The binary encoding for instructions is usually divided into different fields; with each field representing part of the information needed by the instruction.Our instructions require two fields: Operation Code and DataOpcode | DataHow many bits for the Opcode? Have 3 instructions, need at least 2 bits! (2 bits can encode 22items)How many bits for Data? The data field must specify the 4 bits for the SSN number, and also specify a memory location. For now, lets use 4 bits for data. Instruction is 6 bits total.Opcode | DataI5 I4 I3 I2 I1 I06BR 6/00 16Instruction Table0 0 | 4-bit locationJMP locationI5 I4 I3 I2 I1 I00 1 | 4-bit locationJC location1 0 | 4-bit dataOUT dataNote that Opcode = 11 is unused.Also, the opcode assignments were arbitrary; we could have easily chosen some other assigment (such as OUT=00, JC=00, JMP=01)BR 6/00 17A Program for SID = 458 70 2198Start: JC odd_start ; jmp only if odd input=1OUT 4OUT 8OUT 0OUT 2OUT 8JMP StartOdd_start: OUT 5OUT 7OUT 1OUT 9JMP Start BR 6/00 18Convert Program to Binary, Put in MemoryJMP Start (loc 0)00 00000BOUT 910 10010AOUT 110 000109OUT 710 011108Odd_start: OUT 510 010107JMP Start (loc 0)00 000006OUT 8 10 100005OUT 210 001004OUT 010 000003OUT 810 100002OUT 410 010001Start: JC Odd_start (loc 7)01 011100InstructionMem ContentsMem Location7BR 6/00 19Add Decode Logic to Execute Instructions4ssn[3:0]Data[3:0]4ldREGaclrMEMData[5:0]Addr[3:0]4ldcntrenaclrData[3:0]DECODEData[5:4]c_enc_ldr_ldoddOp[1:0]BR 6/00 20What is Decode Logic?Decode logic controls count register, out register based on Op code value (op[1:0] = Data[5:4]).When does out register get loaded? When OP = 10!! (OUT instruction):VHDL:r_ld <= ‘1’ when ( op = “10”) else ‘0’;When does Counter Load? When JMP
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