1V 0.1 1Memory Vocabulary• ROM – Read Only Memory - a type of memory that cannot be written, can only be read. Contents determined a manufacture time.–ROM is non-volatile – contents remain even when power is off.• PROM – Programmable ROM – a type of memory whose contents can be programmed by the user– OTP – One Time Programmble, a PROM is OTP if contents can be programmed only once. • EEPROM – Electrically Eraseable PROM –contents be erased electrically by the user.– Memory is not alterable under ‘normal’ operation.V 0.1 2Memory Vocabulary• RAM – Random Access Memory – memory that can be both read and written during normal operation.– Contents are non-volatile, will be lost on power off.• SRAM – static RAM – has the following characteristics:– Read, Write operations take equal amounts of time– Access to any ‘random’ location takes same amount of time.– Fastest access time of memory types.– Basic memory cell is a latch, takes 6 transistors per memory bit.V 0.1 3Static Random Access Memory (SRAM)• The serial EEPROM had low pin count because of serial I2C interface– Speed was sacrificed– Random access read took 5 bytes (3 bytes to set address, 2 bytesfor read). Total of 45 bit times (5 * 9), @400 KHz this took 2.5 µs * 45 = 112.5 µs!– Write speed was slow because non-volatile memory (page write took about 6.5 ms for 64 bytes, or about 101 µ s/byte.• An SRAM (Static Random Access Memory) has:– equal read/write times, measured in nanoseconds– volatile (contents not maintained when power removed)– equal cycle time, access time– typically has a parallel interfaceV 0.1 4Typical SRAM Control LinesMEMData[N-1:0]Address[log2(K)-1:0]K x NCSOEWChip Select – must be asserted before Memory will respond to read or write operation. If negated, data bus is high impedance.OE – Asserted for read operation, Memory will drive data lines. W – Asserted for a write operation (Memory inputs data from data pins, processor writes to memory).Data bus is bidirectionalV 0.1 5Sense AmpsBit lines(2 per column)CellWord lines(1 per row)Row DecodeRow AddressColumn DecodeColumn AddressData linesBit Line BiasMemoryOrganizationInternal ArchitectureV 0.1 6Static Ram CellB (bitline) BB (bitline_bar)Wordline2V 0.1 7Cypress 8K x 8 SRAMMultiple Chip Enables – more flexibilityData bus is bi-directional (8 I/O lines).Note: a more precise name for this memory is AsynchronousSRAM. It has no clock input, any change on address inputs accesses a new location.V 0.1 8Read CycleCycle Time – how fast can I start another operation?Access Time – how fast is data ready?For SRAMs, Cycle Time = Access Time, this is a feature ofSRAMs.V 0.1 9Write CycleV 0.1 10Write TimingsNotice that Write Cycle = Read Cycle.All volatile RAM types have this feature.V 0.1 11PIC To SRAM8Kx8IO[7:0]CE2OE#WE#A[7:0]A[12:8]RA[7:0]RB[4:0]RC[7:0]VddCE1#RD0RD1To read: Address on RA, RB. RC port is all inputs; RD0 = ‘0’,RD1 = ‘1’.To write: Address on RA, RB. RC port is all outputs; RD0 = ‘1’, RD1 = 0.‘#’ means low trueV 0.1 12Expanding Memory8Kx8IO[7:0]CE2OE#WE#A[7:0]A[12:8]RA[7:0]RB[4:0]RC[7:0]CE1#RD0RD18Kx8IO[7:0]CE2OE#WE#A[7:0]A[12:8]CE1#RAM1RAM0RB5RAM1 accessed when RB5 = 1RAM0 accessed when RB5 = 03V 0.1 13More MemoryIO[7:0]OE#WE#A[12:0]RA[7:0]RB[4:0],RC[7:0]RD0RD1CE1#RAM0RB[6:5]138IO[7:0]OE#WE#A[12:0]CE1#RAM1IO[7:0]OE#WE#A[12:0]CE1#RAM2IO[7:0]OE#WE#A[12:0]CE1#RAM3201232-to-4 decoderRB[6:5]=00RB[6:5]=01RB[6:5]=10RB[6:5]=11chip select decodingV 0.1 14Memory Map1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0RB[4:0],RA[7:0]RB[6:5]Total memory = 4 * 8K = 32 K ( 25* 210), 15 address lines 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 1 1 1 1 1 1 1 1 1 1 1 Selects chipSelects location within chip0x0000 low RAM00x1FFF high0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x2000 low RAM10x3FFF high1 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0x4000 low RAM20x5FFF high1 1 0 0 0 0 0 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x6000 low RAM30x7FFF highV 0.1 15Other SRAM Types• SSRAM - Synchronous SRAM– Has a clock input– Address, data lines latched on clock edge– Can perform burst cycles• What is a burst cycle?– After first data value is output based upon address, data values in successive locations are output without needing to change address bus– Internal counter used for address valueV 0.1 16Synchronous SRAM (SSRAM)Note clock lines to SRAM. A DDR (Double Data Rate) SSRAM means that data is clocked on both clock edges.V 0.1 17SSRAM Normal Cycle vs Burst CycleAddress ready,Data ready in clocks.Address ready, 1stdata ready in 2 clocks, successive locations ready in successive clocks. This burst cycle is a 2-1-1-1 cycle. Diagram shows burst suspended for 1 clock between 3rd& 4thclock. Normal 2-1-1-1 burst takes 5 clocks.V 0.1 18Why Burst Cycles?• Burst Cycles more efficient at block memory transfers (memory location is successive locations)– Normal cycle would take 8 clocks to transfer data from 4 locations.– 2-1-1-1 burst takes only 5 clocks.• Why do we want to transfer blocks of memory efficiently?– For cache fill operations.– So what is a cache?4V 0.1 19A Cache SystemCPUMemory (SRAM)Single chip(die)Memory (SSRAM)Processor ModuleCasingMemory (SSRAM)Main Memory (DRAM)Motherboard1stlevel cache2ndlevel cache3rdlevel cacheV 0.1 20What is a Cache?• The “closer” a memory is to a CPU, the faster the data transfer between CPU and Memory.– Can’t get any closer than on the same chip as the CPU!• For high performance microprocessors, need LOTS of memory• Don’t have enough room to put all memory on same chip as CPU– Put some memory on same die as CPU, will not be able to hold all needed data/programs but will hold most frequently used data/programs– Will need to swap out some data if we don’t find what we need in the cache (a miss!).V 0.1 21Memory HierarchyRegistersCacheMain MemoryFixed DiskTapeFloppyZipCD-ROMCD-RWRCost/BitAccess/SpeedCapacityThe further away, the cheaper per bit.The further away, the slower the access time, the higher the capacity (density).V 0.1 22cache and memory account for about 70% of the die.Intel 3rdGeneration IA-64 (executes new 64-bit instructions)0.13µL1 instr. cacheIA-32 CPU (pentium, for compatibility)L2 cacheL3 cacheV 0.1 23Main Memory and DRAM• For main memory, we need a memory whose primary characteristics are:– Dense (lots
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