Synchronous Serial IOSerial Peripheral Interface (SPI)I2C (Inter-Integrated-Circuit) BusI2C FeaturesI2C Bus TransferExample: I2C Serial EEPROMI2C Device AddressingWrite Operation – can send up to 64 bytesSpeed ComparisonPolling for end-of-writeRead OperationsPIC18Fxx2 I2C RegistersI2C on the PIC18xx2Lab #9: Read/Write to Serial EEPROMi2cmsu.c SubroutinesWatchdog Timer Usei2c_idle()i2c_start()/i2c_stop()i2c_put()i2c_get()i2c_ack(unsigned char ackbit)i2c_init()An I2C Transaction24LC515 EEPROM Utility Functionsi2c_memread()i2c_memread() continuedi2c_memwrite()i2c_memwrite() continueEEPROM Test: i2cmemtst.cLab 9: I2C & Serial EEPROMISR FlowchartStreaming Write Loop: main()What do you have know?V 0.9 1Synchronous Serial IO• Send a separate clock line with data– SPI (serial peripheral interface) protocol–I2C (or I2C) protocol• Encode a clock with data so that clock be extracted or data has guaranteed transition density with receiver clock via Phase-Locked-Loop (PLL)– IEEE Firewire (clock encoded in data)– USB (data has guaranteed transition density)V 0.9 2Serial Peripheral Interface (SPI)SDI: data inSDO: data outSCK: clock© Thomson/Delmar Learning 2005V 0.9 3CKE configuration bit allows either falling or rising edge of clock to be used, while CKP selects clock polarity. The SMP bit determines if the SDI input is sample in middle or end of the clock period.© Thomson/Delmar Learning 2005V 0.9 4© Thomson/Delmar Learning 2005Multiple SPI peripherals each require a separate chip select line via parallel port line. We will concentrate on the I2C serial bus as it does not require use of chip selects.V 0.9 5I2C (Inter-Integrated-Circuit) BusI2C is a two wire serial interface.SDASCL18F242Microchip 24LC515SDAA2SCLA1A0Vdd10K10KVddSDAA2SCLA1A0SCL – clock lineSDA – data (bidirectional)V 0.9 6What is a bus??© Thomson/Delmar Learning 2005One transmitter over a common channel to one or more receiversV 0.9 7Ethernet is a example of a bus© Thomson/Delmar Learning 2005V 0.9 8I2C Features• Multiple receivers do not require separate select lines as in SPI– At start of each I2C transaction a 7-bit device address is sent– Each device listens – if device address matches internal address, then device responds• SDA (data line) is bidirectional, communication is half duplex• SDA, SCLK are open-drain, require external pullups – Allows multiple bus masters (will discuss this more later).V 0.9 9pullups are needed I2C Bus Addressing© Thomson/Delmar Learning 2005No chip selects needed!!!!!V 0.9 10I2C Bus Transfer© Thomson/Delmar Learning 2005Multiple bytes sent in a transaction; every 8 bits has a 9thbit that is an acknowledge.V 0.9 11Write (master to slave)Read (master from slave)Master initiates all transactions, read or write.© Thomson/Delmar Learning 2005V 0.9 12Example: I2C Serial EEPROMWill use the Microchip 24LC515 Serial EEPROM to discuss I2C operation.The 24LC515 is a 64K x 8 memory. This would require 16 address lines, and 8 data lines if a parallel interface was used, which would exceed the number of available IO pins our PIC18F242!!!Putting a serial interface on a memory device lowers the required pin count. Reduces speed since data has to be sent serially, but now possible to add significant external storage to a low pin-count micro controller.V 0.9 13I2C Device AddressingEach I2C device has either a 7-bit or 10-bit device address.We will use an I2C EEPROM and an I2C DAC (Digital-to-Analog Converter, MAX517) in lab. Both of these devices have a 7-bit address.Upper four bits are assigned by device manufacturer and are hardcoded in the device. Lower three bits are used in different ways by manufacturer.Microchip 24LC515SDAA2SCLA1A0LC515 control byte (contains slave address):7 6 5 4 3 2 1 0 1 0 1 0 B0 A1 A0 R/W‘B0’ is block select (upper/lower 32K). A1, A0 are chip selects, four devices on one bus.R/W = 1 for read, 0 for write.V 0.9 14Write Operation – can send up to 64 bytes• Send up to 64 bytes, then perform write– Send starting address, followed by 64 bytes– After 64 bytes sent, wait 5 ms for write to complete– Much faster than individual writesAddress should be on a page boundary when writing a block of 64 bytes. For page size = 64 = 0x40, starting address should be a multiple of 64. A stop condition halts the write.V 0.9 15Speed Comparison• Assume a 400 Khz I2C bus, 2.5 us clock period (2.5 e-6)• Writing one byte at a time:– 9 bit transmission = 2.5 us * 9 = 22.5 us– 5 ms + 22.5 us* 4 (control,addhi,addlo,data) =5.09 ms– For 64 bytes = 325 ms approximately, not counting software overhead.• Writing 64 bytes at a time– 67 bytes total (control, addhi, addlo, data)– 5 ms + 67 * 22.5 us = 6.5 ms!!!V 0.9 16Polling for end-of-writeTiming on write is guaranteed to finish after 5 ms. But can end sooner; to determine if write finished use polling method.© Thomson/Delmar Learning 2005A NAK means device is still busy with last write.V 0.9 17Read Operations© Thomson/Delmar Learning 2005V 0.9 18PIC18Fxx2 I2C Registers• Synchronous Serial Port on PIC18Fxx2 implements I2C• Registers are:– SSPCON – control register - we will always set this to 0x28 which enables I2C MASTER mode.– SSPCON1 – control register - used to initiate a START/STOP conditions, indicates if ACK has been received– SSPSTAT – status register – check this to see if byte finished transmitting, or byte has been received– SSPBUF – read/write to this register for data transfer– SSPADD – used to control clock rateV 0.9 19I2C on the PIC18xx2• Will always use master mode on the PIC18Fxx2– This means that the PICFxx2 will always initiate all I2C bus activity•To set I2C clock rate, write 8-bit value to the SSPADD register– Clock rate = Fosc/(4 *(SSPADD+1))•I2C standard defines 100 KHz and 400 KHz but in reality just about any clock rate from DC to 400 KHz worksClock Rate formula in SSPCON1 description, page 136 of datasheet (page 138 PDF page), section 15-4 of datasheetV 0.9 20Lab #9: Read/Write to Serial EEPROM• Lab #9 has you read/write to a Serial EEPROM via the I2C bus• The files i2cmsu.h, i2cmsu.c define interface subroutines for the I2C bus•This file i2c_memutil.c has subroutines for random read/write, block read/write for the serial eeprom• The file i2cmemtst.c tests uses the subroutines to read/write data to the serial EEPROM.V 0.9 21i2cmsu.c Subroutines• i2c_idle() – wait for idle condition on I2C
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