1Computer Interrupta signal indicating that an event needing immediate attention has occurred2 Types of Interrupts:External - generated outside CPU by other hardwareInternal - generated within CPU as a result of an instruction or operation- x86 has internal interrupts: int, into, Divide Error and Single Step- Trap generally means any processor generated interrupt- in x86, Trap usually means the Single Step interrupt x86 Interrupts:1) Hardware Interrupt - External Uses INTR and NMI2) Software Interrupt - Internal - from int or into3) Processor Interrupt - Traps and 10 Software Interrupts (12 total)8086/8088 Pinout DiagramsGNDAD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0NMIINTRCLKGNDVCCAD15A16/S3A17/S4A18/S5A19/S6HOLDHLDAALEREADYRESETBHE/S7MN/MXRDWRM/IODT/RDENINTATEST123456789101112131415161718192031302928272625242322214039383736353433328086GNDA14A13A12A11A10A9A8AD7AD6AD5AD4AD3AD2AD1AD0NMIINTRCLKGNDVCCA15A16/S3A17/S4A18/S5A19/S6HOLDHLDAALEREADYRESETSS0MN/MXRDWRIO/MDT/RDENINTATEST1234567891011121314151617181920313029282726252423222140393837363534333280888086 8088Mode ModePinMinimum MaximumPinMinim um Maximum31 HOLD RQ/GT0 31 HOLD RQ/GT030 HLDA RQ/GT1 30 HLDA RQ/GT129 WR LOCK 29 WR LOCK28 M/IO S2 28 IO/M S227 DT/R S1 27 DT/R S126 DEN S0 26 DEN S025 ALE QS0 25 ALE QS024 INTA QS1 24 INTA QS134 SS0 High State*Minimum/Maximum Mode Refers to the Bus Handshaking8086 Interrupt ConnectionsNMI - Non-Maskable Interrupt INTR - Interrupt RequestInterrupt LogicintintoDivideErrorSingleStepNMI Requesting Device8086 CPUIntel8259APICNMIINTRSoftware TrapsProgrammable Interrupt Controller (part of Chipset)2Interrupt Vector Table - IVT• x86 Recognizes 256 Different Interrupts– Specified by Type Number or Vector• 1 Byte of Data Must Accompany Each Interrupt Specifies Type• Vector is Pointer into Interrupt Vector Table, IVT– Stored in Memory from 0000:0000 to 0000:03ffh• IVT Contains 256 Far Pointer Values–Far Pointer is CS:IP Values• Each Far Pointer is Address of Interrupt Service Routine, ISR– Also Referred to as Interrupt Handler• Table 4-6 of Uffenbeck (3rdedition, pg 197) has the interrupt vector numbers for the 80x86 familyIVT FormatOffsetOffsetOffsetSegmentSegmentSegmentInterrupt 0Interrupt 1Interrupt 2550000:00000000:00010000:00020000:00030000:00040000:00050000:00060000:00070000:03fc0000:03fd0000:03fe0000:03ffIP LSBIP MSBCS LSBCS MSBGiven a Vector, where is the ISR address stored in memory ?4Offset Type=×Example: int 36hOffset = (54×4) = 216 = 00d8hWhat Happens During an Interrupt ?CompleteCurrentInstructionInternal IntrNMIINTRTFExecuteNextInstructionIFAcknowledgeInterruptRead TypeCodePushFlagsSetTEMP=TFIF=0TF=0PushCS and IPcallISRNMITEMPExecuteISRpopIP and CSpopfResumeInterruptedProcedureYESYESYESYESNONONONO0110013Similarity to Subroutine Procedurecall ⇔ intret ⇔ iret• call pushes CS, IP and loads CS:IP with address of subroutine• int does what call does and more• ret pops IP, CS• iret pops FLAGS, IP, and CSThis is why ALL programs MUST have a stack segment, so that interrupts can be handledInterrupt Acknowledge CyclesThe interrupt vector number for NMI is 2, so the location in the IVT for the NMI ISR address is 4*2 = 0x00008h.Examination of Table 4-6 in Uffenbeck (3rdedition, pg 196) does not give an interrupt vector number for the INTR interrupt! What is the vector number for INTR?Upon receipt of an INTR interrrupt, the 80x86 executes a two special bus cycles called an Interrupt Acknowledge Cycle. The purpose of an Interrupt Acknowledge Cycle is to fetch the interrupt vector number from the interrupting device via the D7-D0 lines.Interrupt Acknowledge Cycles (cont)The first INTA cycle (2 clks) asserts the INTA# line and alerts the interrupting device that it must be ready to provide the vectornumber. The 2ndINTA cycle (2 clks) asserts the INTA# line and the interrupting device must provide the vector number via the lower 8 data lines (D7-D0). The 80x86 inputs the vector number, and then provides with normal interrupt processing.Some external device like the 8259 PIC isused to satisfy the INTA cycle.Intel8259APICProgrammable Interrupt Controller (part of Chipset)8086INTA#D7-D04halt Instruction• This instruction causes processor to enter a HALT state• HALT state is one where no further instructions are fetched nor executed until one of the following events occurs:1) System is Reset - Rising Edge on RESET pin2) External Interrupt OccursCPU Asset ContentFLAGS Register0000hIP 0000hCS ffffhDS 0000hSS 0000hES 0000hInstruction Queue EmptyInterrupt Vector AssignmentsType Function Comment0 Divide Error Processor - zero or overflow1 Single Step (DEBUG) Processor - TF=12 Nonmaskable Interrupt Pin Processor - NMI Signal3 Breakpoint Processor - Similar to Sing Step4 Arithmetic Overflow Processor - into5 Print Screen Key BIOS - Key Depressed6 Invalid Opcode Processor - Invalid Opcode7 Coprocessor Not Present Processor - no FPU8 Time Signal BIOS - From RT Chip (AT - IRQ0)9 Keyboard Service BIOS - Gen Service (AT - IRQ1)A - F Originally Bus Ops (IBM PC) BIOS - (AT - IRQ2-7)10 Video Service Request BIOS - Accesses Video Driver11 Equipment Check BIOS - Diagnostic12 Memory Size BIOS - DOS Memory13 Disk Service Request BIOS - Accesses Disk Driver14 Serial Port Service Request BIOS - Accesses Serial Port Drvr15 Miscellaneous BIOS - Cassette, etc.16 Keyboard Service Request BIOS - Accesses KB DriverInterrupt Vector Assignments (cont)Type Function Comment17 Parallel Port LPT Service BIOS - Printer Driver18 ROM BASIC BIOS - BASIC Interpreter in ROM19 Reboot BIOS - Bootstrap1A Clock Service BIOS - Time of Day from BIOS1B Control-Break Handler BIOS - Keyboard Break1C User Timer Service BIOS - Timer Tick1D Pointer to Video Parm Table BIOS - Video Initialization1E Pointer to Disk Parm Table BIOS - Disk Subsystem Init.1F Pointer to Graphics Fonts BIOS - CGA Graphics Fonts20 Program Terminate DOS - Clear Memory, etc.21 Function Call DOS - Transfer Control22 Terminate Address DOS - program Terminate handler23 Control-C Handler DOS - For OS Use24 Fatal Error Handler DOS - Critical Error25 Absolute Disk Read DOS - Disk Read26 Absolute Disk Write DOS - Disk Write27 Terminate DOS - TSR Usage28 Idle Signal DOS - Idle2F Print Spool DOS - Cassette, etc.70-77 Hardware Interrupts in AT Bios DOS - (AT - IRQs 8-15)5AT – IRQ DefinitionsIBM-AT (Advanced Technology) - Intel 80286)Name Interrupt Vector Priority Description NMI 02 1 Memory Parity Error IRQ0 08 2 Timer (Intel
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