1V 0.1 1Digital Signal ProcessingVref0TimeAnalog signal (time varying, continuous) Analog-to-Digital Converter (ADC)0x030, 0x4A, 0x12, 0xAF, etc.Incoming samplesµProcessorperforms computation0x0B3, 0x23, 0xCF, 0x78, etc.Outgoing samples0TimeVrefnew waveformDigital-to-Analog Converter (DAC)V 0.1 2Applications• Audio– Speech recognition– special effects (reverb, noise cancellation, etc)•Video– Filtering– Special effects– Compression• Data loggingV 0.1 3Vocabulary• ADC (Analog-to-Digital Converter) – converts an analog signal (voltage/current) to a digital value• DAC (Digital-to-Analog Converter) – converts a digital value to an analog value (voltage/current)• Sample period – for ADC, time between each conversion– Typically, samples are taken at a fixed rate• Vref (Reference Voltage) – analog signal varies between 0 and Vref, or between +/- Vref• Resolution – number of bits used for conversion (8 bits, 10 bits, 12 bits, 16 bits, etc).• Conversion Time – the time it takes for a analog-to-digital conversionV 0.1 4Digital-to-Analog ConversionFor a particular binary code, output a voltage between 0 and VrefDACD[7:0]VoutVrefAssume a DAC that uses an unsigned binary input code, with 0 < Vout < Vref. ThenD= 0000 0000 Vout = 0VD= 0000 0001 Vout = Vref(1/256 ) (one LSB)D = 0000 0010 Vout = Vref(2/256)...D = 1111 1111 Vout = Vref(255/256) (full scale)V 0.1 5DAC Output Plot01231/256 VrefInput code2/256 Vref3/256 Vref4/256 VrefVoutOutput signal increases in 1 LSB increments.V 0.1 6Typical DAC OutputFrom http://www.allaboutcircuits.com2V 0.1 7DAC ArchitectureOperational Amplifier can be used to sum voltages.From http://www.allaboutcircuits.comV 0.1 8DAC Architecture (cont)Note ratios of resistorsThis is a binary codeFrom http://www.allaboutcircuits.comV 0.1 9DAC Architecture (cont)A 3-bit DAC, called an R/2NR DAC. Resistors are scaled by powers of 2 (this is hard to do in practice).From http://www.allaboutcircuits.comV 0.1 10Another ViewResistance values are still R, 2R, 4RFrom http://www.allaboutcircuits.comV 0.1 11R/2R DAC Via circuit analysis, can prove this is an equivalent circuit.Now only need resistances of R, 2R –this is easy to do. This is the most common DAC architecture.From http://www.allaboutcircuits.comV 0.1 12Commercial DACs• Either voltage or current DACs– Current DACs require an external operational amplifier to convert to voltage• Precision up to 16-bits• Key timing parameter is settling time - amount of time it takes to produce a stable output voltage once the input code has changed• We will use an 8-bit voltage DAC with an I2C interface from Maxim semiconductor3V 0.1 13DAC ApplicationVertical DeflectionHorizontal DeflectionElectron Beams (Red, Green Blue)PhosperGridCathodeDAC8DAC8DAC8RedGreenBlueRGBHigh speed video DACs produce RGB signals for color CRTV 0.1 14A 1-bit ADCVref+-VinRRVref/2Vout=Vdd is Vin > Vref/2Vddanalog signalVout=0 if Vin < Vref/2digital signalcomparatorV 0.1 15A 2-bit ADC+-+-+-RRRRVinVinVin1/4Vref1/2Vref3/4VrefCBAA B C D1 D0-------------0 0 0 0 00 0 1 0 10 1 1 1 01 1 1 1 1(other codesdon’t cares)D[1:0]Encoding logicV 0.1 16ADC Architectures• The previous architectures are called Flash ADCs– Fastest possible conversion time– Requires the most transistors of any architecture– N-bit converter requires 2N-1 comparators.– Commercially available flash converters up to 12 bits.– Conversion done in one clock cycle• Successive approximation ADCs– Use only one comparator– Take one clock cycle per bit– High precision (16-bit converters are available)V 0.1 17Successive Approximation ADCFirst, set DAC to produce Vref/2. Output of Comparator is Q[N-1] (MSB)If MSB =1 , then Vin between Vref and Vref/2, so set DAC to produce ¾ Vref.If MSB=0, then Vin between Vref/2 and 0, so set DAC to ½ Vref.Output of comparator is now Q[N-2].Do this for each bit.Takes N cycles.Output is Q[N].From http://www.allaboutcircuits.comV 0.1 18Commercial ADCs• Key timing parameter is conversion time – how long does it take to produce a digital output once a conversion is started• Up to 16-bit ADCs available • Separated into fast/medium/low speed families– Serial interfaces common on medium/low speed ADCs• For high-precision ADCs, challenge is keeping system noise from affecting conversion– Assume a 16-bit DAC, and a 4.1V reference, then 1 LSB = 4.1/216= 62 µV.4V 0.1 19PIC16 A/D• PIC16F873 has onboard A/D– Successive approximation– 10 bit resolution– Reference voltage can be Vdd or separate voltage– Multiple input (more than one input channel)– Time per bit(Tad) for conversion is either 2Tosc, 8Tosc, or 32 Tosc, where Tad cannot be less than 1.6 us (Tosc = 1/Fosc)• Total conversion time is 10* Tad +Taq (acquisition) – Taq is approximately 20 us; acquisition time is the amount of time input capacitor requires to charge up to input voltage.– So a 20 Mhz Fosc, Tosc = .05 us, so 32Tosc = 1.6 us; conversion time = 10*1.6 us + 20 us = 36 us.V 0.1 20Input PinsAnalog input channels (AN0,AN1, AN4)Can be analog input channels or Vref+/Vref-V 0.1 21A/D Block DiagramChannel select analog mux.Vref+/Vref- select V 0.1 22Acquisition TimeAcquisition time is the time required for the analog input voltage to be sampled by the input capacitor. The sampling switch is CLOSED during this time.When the conversion begins, the sampling switch is OPENED and the input capacitor holds the input voltage while the conversion is done. This process is also called sample and hold.V 0.1 23Voltage ReferencesStability of voltage reference is critical for high precision conversions.We will use Vdd as our voltage reference for convenience, but will be throwing away at least two bits of precision due to Vdd fluctations. Example Commercial voltage reference: 2.048v, 2.5v , 3v, 3.3v, 4.096v, 5v (Maxim 6029)5VVdd Vref4.096vKey parameter for a voltage is stability over temperature operating range. Need this to be less than ½ of a LSB value.V 0.1 24PIC A/D Registers• ADCON0, ADCON1 – configuration registers– ADCON1 used to configure port A for analog/digital inputs, voltage reference– ADCON0 used for clock selection, analog input selection, start/finish conversion status.• ADRESH, ADRESL -10-bit results returns in two registers– 10-bit result can be configured to be left or right justified.ADRESH : ADRESL DDDDDDDD DD98765432 10000000Left justifiedADRESH :
View Full Document
Unlocking...