ADC differences with and without DMAAutomated Channel Scanning with DMAPing-pong BufferingSimultaneous Sampling ExampleSummaryThe ADC Module with DMA Appendix H 1 Appendix H The ADC Module with DMA This appendix discusses the ADC operation on PIC24 CPUs that have DMA. The ADC material in Chapter 11 is focused on PIC24 CPUs without DMA. This appendix assumes that the reader has covered the material in Chapter 11 on ADC operation and in Chapter 13 on the DMA module. This appendix frequently refers to figures in Chapters 11 and 13. ADC DIFFERENCES WITH AND WITHOUT DMA As discussed in Chapter 13, some PIC24 CPUs support a DMA module. For example, the PIC24HJ32GP202 CPU used in Chapter 11 that discusses ADC operation does not support DMA, while the PIC24HJ64GP502 used in Chapter 13 does have the DMA module. The ADC module in DMA-capable PIC24 CPUs operates differently in some modes than what is discussed in Chapter 11. In referring to Figure 11.7, the ADC module in a PIC24 CPU with DMA does not have ADC buffers 1 through F (registers ADCxBUF1 through ADCxBUFF). What this means is that ADC operation that only involves a single conversion where the result is placed in ADCxBUF0 is the same regardless of whether DMA is supported or not. Thus, the example code in Figure 11.14 and the convertADC1() function of Figure 11.13 operates the same way regardless of whether DMA is supported or not. However, modes that automatically perform multiple conversions, such as the scan mode, operate differently on PIC24 CPUs with DMA. In these cases, the DMA module must be used to store the multiple ADC conversion results instead of them being placed in the ADCxBUF1 through ADCxBUFF registers. The DMA module gives more flexibility in terms of the number of conversions performed and how they are stored in memory. The ADC code examples in Figures 11.17/19 (automatic scanning), Figure 11.21 (automatic scanning), Figure 11.22 (automatic scanning with ping-pong buffers), and Figures 11.25/11.26 are not appropriate for PIC24 CPUs with DMA. AUTOMATED CHANNEL SCANNING WITH DMA Our first example uses the same hardware setup as described in Figure 11.16. Our goal is to perform automated channel scanning on seven ADC inputs (AN0, AN1, AN4, AN5, AN10, AN11, AN12). In the code example of Figure 11.17, we noted that these results were placed in ADC registers ADCxBUF0 through ADCxBUF6 and that the ADC ISR interrupt occurred after the seven conversions had been completed. The ADC ISR then copied the registers to a memory buffer named au16_buffer[]. The main() code of Figure 11.19 printed these to the console as shown in Figure 11.20. The presence of the DMA module requires the following changes: A supplement for Microcontrollers: From Assembly Language to C Using the PIC24 Family, by Reese/Bruce/Jones.The ADC Module with DMA Appendix H 2 • The ADC ISR is no longer used, as the ADC interrupt now occurs after each conversion, at which point the DMA module transfers the result to a user-specified DMA buffer. The DMA interrupt is used instead to indicate when the seven conversions have finished and the DMA ISR is used to copy these to another memory buffer. • A DMA channel must be configured to be linked to the ADC module and a buffer in DMA memory allocated for the ADC results. The DMA module is configured for word mode since each ADC result is larger than a byte. • There are two choices for storing the ADC results in DMA memory, conversion order mode or scatter/gather mode. In conversion order mode, the results are stored in DMA memory in the order that the conversions are performed as shown in Figure H.1a. Thus, for our seven ADC inputs we have the following: AN0 is stored at DMA buffer offset 0, AN1 at offset 1, AN4 at offset 2, AN5 at offset 3, AN10 at offset 4, AN11 at offset 5, and AN12 at offset 6. This matches the ordering of Figure 11.20 in which the seven ADC conversions are stored in ADC registers ADCxBUF0 through ADCxBUF6. In scatter/gather mode, results are stored in the DMA buffer at the offset that matches the channel number. Thus, AN0 is stored at offset 0, AN1 at offset 1, AN4 at offset 4, AN5 at offset 5, AN10 at offset 10, AN11 at offset 11, and AN12 at offset 12. Figure H.1 Conversion order mode versus gather/scatter mode for storing ADC results to DMA memory for one conversion per ADC input. A supplement for Microcontrollers: From Assembly Language to C Using the PIC24 Family, by Reese/Bruce/Jones.The ADC Module with DMA Appendix H 3 The ADC module has the capability of performing multiple conversions per ADC input during scanning. Figure H.2 shows the buffer storage using the same channels as Figure H.1, but with four conversions per ADC input. The conversion order mode is more efficient in terms of DMA memory usage since DMA memory is used for those channels not scanned during scatter/gather mode, but these locations have to be allocated. However, scatter/gather mode makes it easy to reference the conversions by input number and conversion number. Figure H.2 Conversion order mode versus scatter/gather mode for storing ADC results to DMA memory for four conversions per ADC input. A supplement for Microcontrollers: From Assembly Language to C Using the PIC24 Family, by Reese/Bruce/Jones.The ADC Module with DMA Appendix H 4 Figure H.3 shows the first part of the configDMA_ADC() function used to configure the ADC and DMA modules for automated scanning operations. This is a modified version of the ADC configuration code found in the Figure 11.17 and also includes DMA memory buffer allocation as originally discussed in Figure 13.4 The configDMA_ADC() function adds two additional parameters over the parameters found in the configADC1_AutoScanIrqCH0() function of Figure 11.17. • u8_useScatterGather: non-zero for scatter/gather mode and zero for conversion order mode. • u8_dmaLocsPerInput: this specifies the number of DMA buffer locations to be used per ADC input and is only used in scatter/gather mode. The ADDMABM bit in AD1CON1 is used to choose between scatter/gather mode (ADDMABM = 0) and conversion order mode (ADDMABM = 1). When using conversion order mode the DMA channel is configured for register post-increment addressing, while peripheral indirect is used for scatter/gather mode. The remainder of the configDMA_ADC() function is given in Figure H.4. Note that the DMA request line (DMA0REQ) is tied to the ADC interrupt, with the DMA address register (DMA0PAD) set to the
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