Bob Reese 7/24/00DRAM 17/24/00 1Motherboard Chipsets■ Provided by CPU manufacturer (Intel, AMD, etc)■ Provide integration of several common functions◆ Cache Controller◆ PCI Bus Interface◆ Dram Controller◆ Bridges to other busses✦ ISA, USB, etc.■ Used to be provided by third party vendors but these could not keep up with complexity of new CPUs, also hard to make time to market goals.7/24/00 2Typical PCI Based x86 Computer ArchitectureL3CacheL1Cachex86CPUL2CacheCommon PackageSystem Bus 64-bitAGP SDRAMNorth BridgePCI Bus 32-bitSouthBridgeEIDE 1EIDE 2XD Bus 8-bitFlash Mem BIOS RTC and CMOSISA Bus 16-bitISA Adapter 1 ISA Adapter 2USB Root Hub 1USB Root Hub 2KBD, PS/2, LPT, UART1, UART2, FloppyPCI Adapter 3 PCI Adapter 4PCI Adapter 1 PCI Adapter 2Bob Reese 7/24/00DRAM 27/24/00 3AMD MotherboardNote that communication between chips in chipset is via PCI bus7/24/00 4Pentium II Motherboard with Intel 440LX ChipsetNote that communication between chips in chipset is via PCI busBob Reese 7/24/00DRAM 37/24/00 57/24/00 6INTEL 820 Chipset (for Pentium III)Bob Reese 7/24/00DRAM 47/24/00 7WinmodemsupportTwo processors supported“Hub” architecture. Dedicated comm link between two chips of chipset7/24/00 8I82802 Firmware Hub■ Optional component for all 810 and above chipsets■ 4 or 8 Mbits of flash memory for non-volatile storage (can be used by BIOS)■ Contains a Random number generator based on thermal noise◆ Actual RNG instead of psuedo-RNG can increase security of encryption algorithmsBob Reese 7/24/00DRAM 57/24/00 9Low Pin Count (LPC) interface■ Intended to be new interface between legacy devices (ISA, X-bus) and chipset■ Devices that interface with chipset thru LPC interface:◆ SuperIO devices (Keyboard, Serial Port, parallel port, Floppy Disk Controller)◆ Generic memory (BIOS)■ Uses PCI 33 Mhz clock■ Goal is a PC without either X-Bus or ISA7/24/00 10Intel 815E Chipset■ Intended for low cost to midstream PCs■ 3D graphics controller (low-performance, based on i740 3D graphics chip) integrated on chipset!■ SDRAM controller■ 2 USB controllers■ AGP port also included – if on-chip 3D controller is used, then AGP port used for texture cache■ LAN controller integrated (10/100 Mbit ethernet)■ All of the other usual stuffBob Reese 7/24/00DRAM 67/24/00 11AGP port can support an external 3D video card815E block diagram7/24/00 12810 Chipset, cheaper version of 815.No AGP port, intended for low cost PCs.Bob Reese 7/24/00DRAM 77/24/00 13AGP - Advanced Graphics Port■ A dedicated, bi-directional, point-to-point bus meant for high speed transfers between the graphics adapter and system memory■ Major problem with graphics card is memory◆ Often need a lot of it (> 8Mb)◆ If this memory is placed on graphics card, then card is expensive.◆ If System memory is used, then access over PCI bus is slow✦ Solution, Add new dedicated bus!!!7/24/00 14AGP Data PathsBob Reese 7/24/00DRAM 87/24/00 15Intel 740 3D Graphics Controller and AGP7/24/00 16Key Features of AGP■ Allows dual edge clocking on 66 Mhz bus◆ Data transferred on BOTH edges of clock (called 2X AGP)◆ Data bandwidth is 4 bytes * 133 Mhz = 533 MB/s◆ AGP 2.0 added 4X mode to increase bandwidth to 1066 MBs■ Implements sideband addressing for transaction commands◆ Separate command bus for transaction commands◆ Can queue up multiple transactions via command bus, data transfer on data bus is continuous as one transaction finishes and another begins.Bob Reese 7/24/00DRAM 97/24/00 17Effect of Sideband Command CapabilitySBA port is a seperate port (8 bits) that contains just command data. Does not have to be used, main data bus can be used to pass all commands/data/addresses.7/24/00 18AGP 2X Transfer -- AD_STBx is driven by chipsetBob Reese 7/24/00DRAM 107/24/00 19AGP 4X Transfer7/24/00 20Characteristics of High Performance Busses■ Wider is better (at least 32-bit data width) ■ Dual edge clocking■ Split Transactions (issue a command to IO device to start transfer), then come back later when data is ready■ Bus Mastership■ Advanced Signaling◆ Limited voltage swing, differential signalingBob Reese 7/24/00DRAM 117/24/00 21Pentium II/III GTL Bus (Host Bus)■ Gunning Transceiver Logic (GTL) used for Pentium II local bus (66Mhz now, 100Mhz, 133 Mhz)◆ GTL bus is open drain bus where all runs are terminated◆ Termination voltage (Vtt) is 1.5 v.■ GTL bus is a differential bus with only wire!◆ Vref used by all receivers, drivers✦ Vref (1.0v) is 2/3 of Vtt .◆ Voltage swing about Vref is +/- 200 mv.✦ Less voltage swing => higher speed, less noise margin7/24/00 22GTL Bus (continued)■ Interconnections on a GTL bus are transmission lines so interconnect topology, termination very important.■ Interconnection is point to point to avoid stubs (stubs generate
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