1V 0.4 1Microcontroller (µC) vs. Microprocessor (µP)• µC intended as a single chip solution, µP requires external support chips (memory, interface)• µC has on-chip non-volatile memory for program storage, µP does not.• µC has more interface functions on-chip (serial interfaces, Analog-to-Digital conversion, timers, etc.) than µP• µC does not have virtual memory support (I.e, could not run Linux), while µP does.• General purpose µPs are typically higher performance (clock speed, data width, instruction set, cache) than µCs• Division between µPs and µCs becoming increasingly blurredV 0.4 2PIC 16F87x µCDC to 20 MhzClock speedAccumulator, 35 instructions ArchitectureAsync serial IO, I2C, SPI, A/D, 16-bit timer, two 8-bit timersOn-chip modulesVaries, up to 368 x 8On-chip Random Access Memory (RAM) Varies, up to 8K x 14 wordsOn-chip program memory (non-volatile, electrically erasable)14 bitsInstruction widthCommentsFeaturesV 0.4 3Accumulator-Based Instruction Set Two operand instructions have the Working Register (w reg) as one operand, and memory or data in the current instruction as the second operand. The destination can be either be wreg or file registers.A register used in the manner of the w register is generally called an accumulator.The instruction register contains the machine code of the instruction currently being executed.DO = data outWALURAM File RegistersInst. Reg8888DO DI7addressDI = data inV 0.4 4The addwf instructionGeneral form:addwf floc, dd← [floc] + wfloc is a memory location in the file registers (data memory)w is the working registerd is the destination, can either be the literal ‘f’ or ‘w’[floc] means “the contents of memory location floc”addwf 0x70,w w ← [0x70] + waddwf 0x70,f [0x70] ← [0x70] + wV 0.4 5addwf ExamplesAssume data memory contents on rightw register contains 0x1DExecute: addwf 0x59, w w ← [0x59] + ww = [0x59] + w = 0xBA + 0x1D = 0xD7After execution w = 0xD7, memory unchanged.Location contents0x580x2CData Memory0x590xBA0x5A0x340x5B0xD3Execute: addwf 0x59, f [0x59] ← [0x59] + w[0x59] = [0x59] + w = 0xBA + 0x1D = 0xD7After execution [0x59] = 0xD7, w is unchanged.V 0.4 6addwf floc, wWALUInst. RegActive data pathsw is a source and destination.RAM File RegistersDO DIaddrAddress/control2V 0.4 7addwf floc, fActive pathsfloc is a source and destination.WALUInst. RegRAM File RegistersDO DIaddrAddress/controlV 0.4 8addwf instruction encodingSee page 136 in PICF87X datasheetaddwf floc, d0 0 0 1 1 1 d f f f f f f fB B B B B B B B B B B B B B1 1 1 1 0 0 0 0 0 0 0 0 0 03 2 1 0 9 8 7 6 5 4 3 2 1 0‘fffffff’ lower 7-bits of floc address‘d’: 0 = w reg, 1 = fMachine code Instruction0x07D9 addwf 0x59, f 0x0759 addwf 0x59, wV 0.4 9Move literal to w (movlw)The previous example assumed that w contained a value of 0x1D. How did this get into w in the first place ?movlw k1 1 0 0 x x k k k k k k k kB B B B B B B B B B B B B B1 1 1 1 0 0 0 0 0 0 0 0 0 03 2 1 0 9 8 7 6 5 4 3 2 1 0“kkkkkkkk” 8-bit constant, loaded into w registerMachine code Instruction0x301D movlw 0x1D Note that the instruction word contains the 8-bit constant, not data memory. w ← kV 0.4 10movlw kActive pathsThe instruction registercontains the machine code of the instruction currently being executed. The k value is from the lower 8 bits of the instruction register.WALUInst. RegRAM File RegistersDO DIaddrAddress/controlV 0.4 11Move w to f (movwf)A common operation is to store w to a location in the file registersmovwf floc0 0 0 0 0 0 1 f f f f f f fB B B B B B B B B B B B B B1 1 1 1 0 0 0 0 0 0 0 0 0 03 2 1 0 9 8 7 6 5 4 3 2 1 0‘fffffff’ lower 7-bits of floc addressMachine code Instruction0x00D9 movfw 0x59 [floc] ← wV 0.4 12movwf flocActive pathsThe w value passes through the ALU unchanged on its way to the RAM register file.WALUInst. RegRAM File RegistersDO DIaddrAddress/control3V 0.4 13Increment (incf)See page 136 in PICF87X datasheetincf floc, d0 0 1 0 1 0 d f f f f f f fB B B B B B B B B B B B B B1 1 1 1 0 0 0 0 0 0 0 0 0 03 2 1 0 9 8 7 6 5 4 3 2 1 0‘fffffff’ lower 7-bits of floc address‘d’: 0 = w reg, 1 = fMachine code Instruction0x0AD9 incf 0x59, f ;[0x59] ← [0x59] +10x0A59 incf 0x59, w ; w ← [0x59] + 1Increment destination by 1V 0.4 14Decrement (decf)See page 136 in PICF87X datasheetdecf floc, d0 0 0 0 1 1 d f f f f f f fB B B B B B B B B B B B B B1 1 1 1 0 0 0 0 0 0 0 0 0 03 2 1 0 9 8 7 6 5 4 3 2 1 0‘fffffff’ lower 7-bits of floc address‘d’: 0 = w reg, 1 = fMachine code Instruction0x03D9 decf 0x59, f ;[0x59] ← [0x59] -10x0359 decf 0x59, w ; w ← [0x59] - 1Decrement destination by 1V 0.4 15How is the instruction register loaded?WALURAM File RegistersInst. Reg8888DO DI7addressDI = data inProgram Counter13addressProgram Memory,non-volatile up to 8K x 14DO14Program counter contains the address of the current instruction being executed. After reset, first instruction fetched from location 0x0000 in program memory.V 0.4 16Goto location (goto)The program counter specifies the location of the current location. How is this changed?goto k1 0 1 k k k k k k k k k k kB B B B B B B B B B B B B B1 1 1 1 0 0 0 0 0 0 0 0 0 03 2 1 0 9 8 7 6 5 4 3 2 1 0“kkkkkkkkkkk” lower 11-bits of a location , loaded into lower 11-bits of the program counter register (PC[10:0));PC[12:11] ← PCLATH[4:3].Machine code Instruction0x2809 goto 0x9 The next instruction is fetched from the target address. PC[10:0] ← kV 0.4 17PCLATH registerPCLATH is a special register located at 0x0A that is used by instructions that modify the PC register.The PC register is 13 bits so programs can be a maximum of 8K (8192) instructions. Instructions that affect the PC only change either the lower 8-bits or lower 11-bits; the remaining bits come from the PCLATH register.If your program is less than 2K (2048) instructions, then you donot have to worry about modifying PCLATH before a gotobecause the PCLATH[4:3] bits will already be ’00’. V 0.4
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