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MSU ECE 3724 - Parallel IO

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1V 0.2 1Parallel IOParallel IO – data sent over a group of parallel wires. Typically, a clock is used for synchronization.CPU #1D[15:0]CPU #2clkA 16-bit data channel is shown above. If data is transferred each rising clock edge, and clock rate is 300 MHz, then the data transfer rate (bandwidth) in bytes/sec is:2 Bytes/clock period = 2 /(1/300e06)s = 2 * 300e06/s = 600e06/s = 600 MB/s (MB = MBytes)V 0.2 2Serial IOSerial IO – data sent one bit at a time, over a single wire. A clock may or may not be used for synchronizationCPU #1CPU #2clkDQuestion: Assuming one bit is sent each rising clock edge, how fast does the clock have to be achieve 600 MB/s? 600 MByte/s = 600 MBytes/s * 8 bits/1Byte = 4800Mb/sClock period = 1/4800e06Clock Frequence = 1/clock period = 4800e06 = 4.8e09 = 4.8GHzV 0.2 3Parallel vs. Serial IOParallel IO Pros/ConsPros: Speed, can increase bandwidth by either making data channel wider or increasing clock frequencyCons: Expensive (wires cost money!). Short distance only – long parallel wire causes crosstalk, data corruption.Serial IO Pros/ConsPros: Cheap, very few wires needed. Good for long distance interconnect.Cons: Speed; the fastest serial link will typically have lower bandwidth than the fastest parallel link. However, for long distances (meters), new fast serial IO standards (USB2, Firewire) have replaced older parallel IO standards.V 0.2 4simplex vs half-duplex vs full-duplexFor communication channelsCPU #1CPU #2simplex: communication in one direction onlyCPU #1CPU #2Half-duplex: communication in either direction, but only one way at a timeorCPU #1CPU #2Full-duplex: communication in both directions at same time.V 0.2 5Wires: Simplex, Half-duplexFor wires:simplex wire: communication occurs only in one direction.half-duplex wire: communication can occur in either direction, but with voltage signaling only one direction at a time.uni-directionalbi-directionalTxRxOeRxTxOeTxRxV 0.2 6Wires: Full DuplexTxRx = ib-+Tx+-Rx = iaiaibia + ibia + ibiaibia + ibCurrent mode signaling allows full duplex communication over a single wire. Used for communication in some advanced chipsets.Currents add, voltages do not!2V 0.2 7Synchronous Serial IO CPU #1Synchronous Serial IO ChannelSynchronous serial IO either (a) sends the clock as a separate wire OR(b) receiver (CPU #2) extracts clock from data stream or uses a Phase-Locked-Loop (PLL) and changes in the data stream to synchronize internal clock (phase alignment) to data stream. For PLL synchronization, the data line must be guaranteed to have a minimum number of state changes (0 → 1 or 1 →0) within a particular time interval (transition density). Synchronous serial IO can achieve high speeds; all new high speed serial standards are synchronous.CPU #2Internal clock frequencies match to within a tolerance value. Can be out of phaseV 0.2 8Asynchronous Serial IOCPU #1Asynchronous Serial IO ChannelCPU #2Internal clock frequencies match to within a tolerance value. Can be out of phaseAsynchronous Serial I/O does not transmit the clock on a separate wire nor does it guarantee a particular transition densisty (ie., the data line could remain in the same state, either ‘1’ or ‘0’ for the duration of the transmission after the initial state change indicating start of transmission).Asynchronous Serial I/O is used in older standards, is easy to implement, but is slower than synchronous serial standards.V 0.2 9A Three-Wire Async Serial Interface We will use a three-wire asynchronous serial interface to connect the PIC to an external PC. This interface standard is known as RS-232 (there are more wires defined in the standard, we will only use 3 wires)CPU #1CPU #2Tx RxRx Txgnd gndTx:transmit, Rx:ReceiveEach wire is simplex, but communication channel is full duplexV 0.2 10Asynchronous Serial Data FrameSerial Data Receiver Starts Processing When:1) high to low is sensed (start bit detection)2) following (7 or 8) bits represent a character3) parity bit for error detection4) stop bit is detected (a “mark”)D0D1D2D3D4D5D6P D0D1***ST**10 bits 7E1 (7 data bits, even parity, 1 stop bit)D0D1D2D3D4D5D6D7D0D1**ST**10 bits 8N1 (8 data bits, no parity, 1 stop bit) *STSTMark – A Constant Logic-1 Denoted by * Space – A Constant Logic-0Standard is for Serial Line to CONSTANTLY be Driven to a MARK While InactiveST– start bit 1 ASCII char. = 7 bitsD0– LSB (e.g. DEL = 7fh – higher is PC specific)D6(D7) – MSB Typical is 10 bits for asynchronous transferP – parity bit Serial data with even/odd parity* - stop bit – a “mark”slide by Prof. Mitch ThorntonV 0.2 11ExampleWhen Receiver “sees” a Start Bit (high to low transition):1) Local Timer Starts2) Each bit sampled at midpoint in time (± % clock tolerance)3) Maximum tolerance is ± ½ of 1 bit time interval over 10 intervals= (½)/10 = 5%0 1 1 0 1 0 1 0 1 1 111 0* - stop bit – a “mark”ST–start bit56h = “V” – ASCII CharacterP – even parity bitdata valuesslide by Prof. Mitch ThorntonV 0.2 12Parity•A parity bit is an extra bit added to a data frame to detect a single bit error– A single bit error is when one bit of the frame was received incorrectly (read as ‘0’ when should have been ‘1’, or vice-versa). – Not guaranteed to detect multi-bit errors• Odd parity – parity bit value makes the total number of ‘1’ bits in the frame odd– For 7-bit data value 0x56 (1010110), odd parity bit = ‘1’• Even parity – parity bit value makes the total number of ‘1’ bits in the frame even– For 7-bit data value 0x56 (1010110), even parity bit = ‘0’3V 0.2 13Receiver Samplingone bit time0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4Receiver clock; period usually either 64x or 16x bit time (above is 16x).At start bit, internal 4-bit counter set to 0. Sample at mid-point of bit time (counter value 7 or 8, some receivers sample at 7,8 and 9 and only accept bit if all values are the same – do this for glitch rejection). Receiver/Transmitter clocks not perfectly matched. Our tolerance is ½ bit time (50%) spread over entire frame. Assuming a 10 bit frame, maximum mismatch between Rx/Tx clocks is 50%/10 = 5%,next bitsample hereV 0.2 14Baud Rate vs Bits Per Second• Baud rate is the rate at which signaling events are sent• Bits per second (bps) is the number of bits transferred per second (any type of bits, data or overhead bits)• If only a ‘1’ or ‘0’ is sent for each signaling event, then baud rate =


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