1BR 6/00 1Recall Basic Memory DefinitionMEMData[N-1:0]Address[log2(K)-1:0]K x NK locations, N bits per locationAddress bus has log2(K) address lines, data bus has N data lines.BR 6/00 2Semiconductor Memory Device Architecture• n×m Device–n inputs called “address lines”– m outputs called “data lines”2×4DecoderA1A0D1D2D3D4D0Storage Cell ArrayBuffers4 x 5 Memory(4 locations, 5 bits per location).BR 6/00 3Additional Control LinesMEMData[N-1:0]Address[log2(K)-1:0]K x NCSOEWChip Select – must be asserted before Memory will respond to read or write operation. If negated, data bus is high impedance.OE – Asserted for read operation, Memory will drive data lines. W – Asserted for a write operation (Memory inputs data from data pins, processor writes to memory).2BR 6/00 4Can see use of CS, W and OE signals.Pentium Memory SystemBR 6/00 5Timing CharacteristicsMemory access time is the time from a valid address being placed on the address bus to valid data appearing on the data bus.Memory write time is the time from a valid address being placed on the address bus to the capturing of the data bus valueby the memory.Faster is better!!!!BR 6/00 6Memory Vocabulary• ROM – Read Only Memory - a type of memory that cannot be written, can only be read. Contents determined a manufacture time.– ROM is non-volatile – contents remain even when power is off.• PROM – Programmable ROM – a type of memory whose contents can be programmed by the user– OTP – One Time Programmble, a PROM is OTP if contents can be programmed only once. • EEPROM – Electrically Eraseable PROM –contents be erased electrically by the user.– Memory is not alterable under ‘normal’ operation.3BR 6/00 7Memory Vocabulary• RAM – Random Access Memory – memory that can be both read and written during normal operation.– Contents are non-volatile, will be lost on power off.• SRAM – static RAM – has the following characteristics:– Read, Write operations take equal amounts of time– Access to any ‘random’ location takes same amount of time.– Fastest access time of memory types.– Basic memory cell is a latch, takes 6 transistors per memory bit.BR 6/00 8Static RAM CellBR 6/00 9Cypress 8K x 8 SRAMMultiple Chip Enables – more flexibilityData bus is bi-directional (8 I/O lines).Note: a more precise name for this memory is AsynchronousSRAM. It has no clock input, any change on address inputs accesses a new location.4BR 6/00 10Read CycleCycle Time – how fast can I start another operation?Access Time – how fast is data ready?For SRAMs, Cycle Time = Access Time, this is a feature of SRAMs.BR 6/00 11Write CycleBR 6/00 12Write TimingsNotice that Write Cycle = Read Cycle.All volatile RAM types have this feature.5BR 6/00 13Other SRAM Types• SSRAM - Synchronous SRAM– Has a clock input– Address, data lines latched on clock edge– Can perform burst cycles• What is a burst cycle?– After first data value is output based upon address, data values in successive locations are output without needing to change address bus– Internal counter used for address valueBR 6/00 14SSRAM Normal Cycle vs Burst CycleAddress ready,Data ready in clocks.Address ready, 1stdata ready in 2 clocks, successive locations ready in successive clocks. This burst cycle is a 2-1-1-1 cycle. Diagram shows burst suspended for 1 clock between 3rd& 4thclock. Normal 2-1-1-1 burst takes 5 clocks.BR 6/00 15Why Burst Cycles?• Burst Cycles more efficent at block memory transfers (memory location is successive locations)– Normal cycle would take 8 clocks to transfer data from 4 locations.– 2-1-1-1 burst takes only 5 clocks.• Why do we want to transfer blocks of memory efficiently?– For cache fill operations.– So what is a cache?6BR 6/00 16A Cache SystemCPUMemory (SRAM)Single chip(die)Memory (SSRAM)Processor ModuleCasingMemory (SSRAM)Main Memory (DRAM)Motherboard1stlevel cache2ndlevel cache3rdlevel cacheBR 6/00 17What is a Cache?• The “closer” a memory is to a CPU, the faster the data transfer between CPU and Memory.– Can’t get any closer than on the same chip as the CPU!• Need LOTS of memory• Don’t have enough room to put all memory on same chip as CPU– Put some memory on same die as CPU, will not be able to hold all needed data/programs but will hold most frequently used data/programs– Will need to swap out some data if we don’t find what we need in the cache (a miss!).BR 6/00 18Cache operations• Hit – memory contents we need is located in cache.• Miss – memory contents we need is not in cache– Check next level of memory to see if it is in the cache. – When we find it, copy in an entire block of memory because if we a particular memory location, chances are that we will need its neighboring locations also very soon.• Transfers between 1stlevel cache and CPU are random accesses, single word transfers.• Transfers between all other memory caches are block oriented – transfer multiple words at a time!7BR 6/00 19x86 Family Burst Cycles8088 - 8 bit data bus, no burst cycles. Read Cycle, Write cycle each took 4 clocks.8086 – 16 bit data bus, no burst cycles. Read Cycle, Write cycle each took 4 clocks.386 – 32 bit bus, no burst cycles, Read Cycle, Write cycle each took 2 clocks.486 - 32 bit bus, Normal Read/Write cycles took 2 clocks. Supports a burst of 2-1-1-1 (5 clocks to read 16 bytes! 32-bit bus transfers 4 byes per bus cycle).Pentium – 64 bit bus, Normal Read/Write cycle takes 2 clocks. Supports a burst of 2-1-1-1 (5 clocks to read 32 bytes).BR 6/00 20Pipelined Bursts• A 486 can only do successive burst cycles that look like:2-1-1-1; 2-1-1-1;2-1-1-1– After one burst is over, must start a complete new burst.• A Pentium can do pipelined burst cycles2-1-1-1;1*-1-1-1;1*-1-1-1The next burst cycle picks up where the previous burst cycle left off!!! No need to supply a new address for the successive burst cycles.BR 6/00 21Memory HierarchyRegistersCacheMain MemoryFixed DiskTapeFloppyZipCD-ROMCD-RWRCost/BitAccess/SpeedCapacityThe further away, the cheaper per bit.The further away, the slower the access time, the higher the capacity (density).8BR 6/00 22Main Memory and DRAM• For main memory, we need a memory whose primary characteristics are:– Dense (lots o’ bits!!!)– Cheap (cause we don’t want to spend too much for our lots o’ bits!)– Good at block transfers, can be rotten at random accesses.• How do we achieve density?
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