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1BR 6/00 1Direct Memory Access (DMA)• Direct Memory Access (DMA) is when a device other than the processor controls the transfer of data between memory and an IO device• A DMA controller is specialized logic that is optimized for this task• A DMA channel is the set of control lines that a DMA controller uses to perform the transfer– DMA controller can have multiple channels so that DMA can be performed for multiple devicesBR 6/00 2DMA (cont).• At a minimum, a DMA operation needs the channel number (which IO device that requires the DMA), a start address in memory for the transfer, the number of bytes to transfer, and the direction of the transfer (from IO to memory, or vice-versa)• The processor kicks off the DMA by a write to a control register in the DMA controller• When DMA is finished, the DMA controller interrupts the processor.• DMA is more efficent at transferring block data between IO device and memory than the CPU -- also, CPU is freed to perform other tasks.2BR 6/00 3Bus Mastership• DMA is an example of where the processor turns control of the bus over to another device• When a device has control of a bus, it is known as the Bus Master• In early system busses, only the processor and DMA controller could have ownership of the bus (become Bus Master)• Modern system busses (e.g. PCI) allow any IO device to become bus master – an IO device that can become bus master can performs DMA to memory itself instead of the DMA controller– If all IO cards can become bus master, then don’t need a seperate DMA controller.BR 6/00 4Bus Arbitration• A piece of control logic known as the ‘arbiter’ must decide which device gets ownership of the bus. This control logic resides in the system chipset.• Two lines are used for each periperal that can assume bus mastership– Bus Request – used by peripheral to ask for control of a bus (input to arbiter)– Bus Grant – used by arbiter to grant the bus to the peripheral (output to arbiter)• A peripheral typically has control of the bus for maximum number number of clock cycles (typically 32) before it has to release control of the bus back to the arbiter.3BR 6/00 5Bus ArbiterArbiterDevice 1Br BgDevice 2Br BgDevice Br BgLocal Bus, e.g PCINumber of Br/Bg pairs determines maximum number of devices on bus (i.e. ‘slots’ on bus)Br: Bus Request, Bg: Bus GrantBR 6/00 6‘Bus’ Terms, Glossary• A ‘Bus’ is a mechanism for multiple devices to talk to one another– When one device ‘talks’, all others ‘hear’• Data can be transmitted in parallel or serially– USB, IEEE Firewire are serial busses– PCI, ISA, SCSI are parallel busses• A bus may support only one bus master, or multiple bus masters– If supports multiple bus masters, will either need to support bus arbitration to decide the master (PCI bus) or schedule the bus access time over the masters (time division multiplexing)4BR 6/00 7‘Bus’ Terms, Glossary (cont)• The System bus is the bus that connects directly to the pins of the processor. Also known as the processor bus.– These days the system bus only has cache memory connected to it and the ‘system chipset’– Multiple processors may connect to the system bus– The system chipset will transfer the data between the system bus and any other busses that are in the system (will act as a bridge between the system bus and other busses).BR 6/00 8‘Bus’ Terms, Glossary (cont)• A local bus is a bus that stays ‘inside the box’ (cards will plug into bus via slots on motherboard) and forms a high speed path between memory and the peripherals– Will be a high bandwidth bus (wide and fast --- parallel bus clocked at high rate)– lines run a short distance– The PCI bus is a local bus– System chipset connects the PCI bus to the procesor (system) bus.5BR 6/00 9‘Bus’ Terms, Glossary (cont)• A Peripheral bus is a bus that goes ‘outside the box’ to connect peripherals to memory. – Will NOT be as high bandwidth as system bus– Will support a wide range of speeds– Can be either serial (Firewire, USB) or parallel (SCSI)– lines can run a long distance compared to system busses– Firewire, USB, SCSI (disks, scanners, CDROMs), EIDE (disks, CDROMs) are peripheral


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MSU ECE 3724 - Direct Memory Access (DMA)

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