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1Processor Architecture Components• Registers : used for storing data values and addresses• Execution units: perform computations (arithmetic, logic) on data – ALU: Arithmetic Logic Unit • Control: logic for fetching, executing instructions• Memory: stores instruction and data• Input/Output: external interface with computer systemProcessor IntegrationEarly computers had many separate chips for the different portions of a computer systemRegistersALUControlMemoryMicroprocessorsFirst microprocessors placed control, registers, Arithmetic logic unit in one integrated circuit (one chip).I/ODevicesMemoryCPU(ALU +Reg +control)Data BusAddress BusControl BusCPU – Central Processing Unit2Modern µProcessorsModern microprocessors (general purpose µProcessors) also integrate memory onchip for faster access. External memory and I/O components still required. Memory integrated on the microprocessor is called cache memory.I/ODevicesMemoryData BusAddress BusControl BusRegisters, ALU,Fetch,Exe Logic,Bus logic,Cache MemoryCPUMicrocontrollersMicrocontrollers integrate all of the components (control, memory, I/O) of a computer system into one integrated circuit. Microcontrollers are intended to be single chip solutions for systems requiring low to moderate processing power.MicrocontrollerIntel x86 Processors• In this course will study the Intel x86 general purpose microprocessor family– Instruction set architecture– Assembly language programming– Hardware features of different x86 implementations– Other features of microprocessor systems3ISA vs Implementation• Instruction Set Architecture (ISA) : the definition of the registers and instructions that define the programmer’s view of a processor (is a text document)• Can have different implementations of the same ISA!– Intel and AMD processors both execute the x86 ISA, but internally are very different!!– Intel has several different implementations of the x86 ISA!• New versions of an ISA extend the previous version by adding instructions, registers – but never invalidate the old ISA!!!!!!!Intel x86 MicroprocessorsCPU Name Year Intro. Int. CPU Clock # Trans. Data Pins Addr Pins8080 1974 2-3 MHz 4500 8 168086 1978 5-10 MHz 29000 16 2080286 1982 6-16 MHz 130000 16 2480386 1985 16-33 MHz 275000 32 3280486 1989 25-50 MHz 1.2M 32 32Pentium 1994 60-200 MHz 3.1M 64 32Pentium Pro 1995 150-200 MHz 5.5M 64 36Pentium MMX 1997 133-266 MHz 64 32Pentium II 1998 233-500 MHz 7.5M 64Celeron 1998 266-500 MHz 7.5M 64Pentium III 1999 450-600 MHz 64Intel x86 Microprocessors8086 - 20 bit Addr. Bus - 1MB of Memory80286 - 24 Addr. Bus - Added Prot. Mode80386 - 32 bit regs/busses - Virtual 86 Mode80486 - RISC Core - L1 Cache - FPUPentium - Superscalar - Dual Pipeline - Split L1 CachePentium Pro - L2 Cache - Br. Pred. - Spec. Exec.Pentium MMX - 57 Instructions - Integrated DSP (MMX)Pentium II - 100 MHz Bus - L2 Cache - MMXCeleron - 66 MHz Bus - True L2 Cache IntegrationPentium III - 100 MHz Bus - 70 Instr. Streaming SIMD Ext.48086/8088 Register FileCSDSSSESAHBHCHDHALBLCLDLIPSPBPSIDI0701507015AccumulatorBaseCounterDataCode SegmentData SegmentStack SegmentExtra SegmentInstruction PointerStack PointerBase PointerSource IndexDestination Index}}}AXBXCXDX8086/8088 Register File (cont)Flags Registerx x x x OF DF IF TF SF ZF x AF x PF x CF015Status and Control Bits Maintained in Flags Register–Generally Set and Tested Individually– 9 1-bit flags in 8086; 7 are unusedStatus FlagsCF Carry Flag Arithmetic CarryOF Overflow Flag Arithmetic OverflowZF Zero Flag Zero Result; Equal CompareSF Sign Flag Negative Result; Non-Equal ComparePF Parity Flag Even Number of “1” bitsAF Auxiliary Carry Used with BCD ArithmeticIndicate Current Processor Status5Control FlagsInfluence the 8086 During Execution PhaseDF Direction Flag Increment/Decrement– used for “string operations”IF Interrupt Flag Enables Interrupts– allows “fetch-execute” to be interruptedTF Trap Flag Allows Single-Step– for debugging; causes interrupt after each op8086/8088 Register File (cont)Instruction Pointer Register015IP Contains Address of NEXT Instruction to be Fetched–Automatically Incremented– Programmer can Control with jump and branchAX, BX, CX, DX General Purpose Registers• Can Be Used Separately as 1-byte RegistersAX ← AH:AL• Temporary Storage to Avoid Memory Access– Faster Execution – Avoids Memory Access• Some Special uses for Certain InstructionsAHBHCHDHALBLCLDL0707AccumulatorBaseCounterData6AX, BX, CX, DX General Purpose Registers - Some Specialized Uses• AX, Accumulator– Main Register for Performing Arithmetic– mult/div must use AH, AL–“accumulator” Means Register with Simple ALU• BX, Base– Point to Translation Table in Memory– Holds Memory Offsets; Function Calls• CX, Counter– Index Counter for Loop Control• DX, Data– After Integer Division Execution - Holds RemainderAHBHCHDHALBLCLDL0707AccumulatorBaseCounterDataCS, DS, ES, SS - Segment Registers Contains “Base Value” for Memory Address• CS, Code Segment– Used to “point” to Instructions– Determines a Memory Address (along with IP)– Segmented Address written as CS:IP• DS, Data Segment– Used to “point” to Data– Determines Memory Address (along with other registers)– ES, Extra Segment allows 2 Data Address Registers• SS, Stack Segment– Used to “point” to Data in Stack Structure (LIFO)– Used with SP or BP– SS:SP or SP:BP are valid Segment AddressesIP, SP, BP, SI, DI - Offset Registers Contains “Index Value” for Memory Address• IP, Instruction Pointer– Used to “point” to Instructions– Determines a Memory Address (along with CS)– Segmented Address written as CS:IP• SI, Source Index; DI, Destination Index– Used to “point” to Data– Determines Memory Address (along with other registers)– DS, ES commonly used• SP, Stack Pointer; BP, Base Pointer– Used to “point” to Data in Stack Structure (LIFO)– Used with SP or BP– SS:SP or SP:BP are valid Segment AddressesThese can also be used as General Registers !!!!!!780386 Register SetGeneral PurposeNote how registers were extended from 16 bits to 32 bits in width.Register EAX refers to the entire 32-bit


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MSU ECE 3724 - Processor Architecture Components

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