1Quantifying Memory• Measured in the quantity of BInary digiT (BIT)1 nybble = 4 bits1 byte = 8 bits1 word = 16 bits1 doubleword = 32 bits1 quadword = 64 bits1 paragraph = 16 bytes1 page = 256 bytes1 segment (max) = 65,636 bytesStandardMachineDependent(8086)• Capacity Measures1 kilobyte (kB) = 210 bytes1 megabyte (MB) = 220 bytes1 gigabyte (GB) = 230 bytes1 terabyte (TB) = 240 bytesModern Computer Model• CPU - Central Processing Unit– arithmetic, logical, synchronization functions• Memory - Stores Information– CPU instructions and Data• I/O - Input/Output Devices - Peripherals– Interface to Outside World (humans, other machines)• Bus - Set of Parallel wires– Transmit instructions/data between CPU/Memory/IOI/ODevicesMemoryCPUData BusAddress BusControl BusDiagram of MemoryCPUMARMDRaddress busMemory (K x M)data busK locationsM bits/locationAddress bus islog2(K) bits wide.K-1K-2...??????7??????6??????5??????3??????2??????1??????0R/Wa[log2(k)-1 : 0]d[M-1:0]MAR: Memory Address Register, holds address of location being accessed.MDR: Memory Data Register, holds incoming/outgoing dataR/W : Read/Write control line, low when writing, high when Reading.28086 Segmented Memory• x86 Memory Partitioned into Segments– 8086: maximum size is 64K (16-bit index reg.)– 8086: can have 4 active segments (CS, SS, DS, ES)– 8086: 2-data; 1-code; 1-stack– x386: maximum size is 4GB (32-bit index reg.)– x386: can have 6 active segments (4-data; FS, GS)• Why have segmented memory ????????Other microprocessors could only address 64K since they only had a single 16-bit MAR (or smaller). Segments allowed computers to be built that could use more than 64K memory (but not all at the same time).8086/8088 Memory Access RegistersCSDSSSESIPSPBPSIDI015015Code SegmentData SegmentStack SegmentExtra SegmentInstruction PointerStack PointerBase PointerSource IndexDestination Index}}}8086 Internal ArchitectureProcessor ModelALUADDAHBHCHALBLCLDLBPDISISPDHCSESSSDSIPInstr. Decode;Bus Controller123456SYSTEM BUS (Internal)FLAGSEUInstructionQueueBIUData BusAddress Bus38086 Generating Physical AddressesADDCSESSSDSIPMemory System Address Lines0000Index Reg. Segment Reg.Physical Address000151519Portion of BIU CircuitryDedicated Segment RegistersDedicated Index RegistersBPDISISPSegmented AddressingCSESSSDSIPBPDISISP• Each Segment must begin at Paragraph Boundary00000h00010h00020hphysical address memoryparagraph 1paragraph 2paragraph 3• Each paragraph has phys. address that is multiple of 10h• BIU is responsible for appending 0000 to Segment– only need 16-bit segment registersSegmented Memory (x86 Style)CSESSSDSDataSegmentStackSegmentExtraSegmentCodeSegmentSegmentRegistersSystemMemory• Segment Registers:– Point to Base Address• Index Registers:– Contain Offset Value• Notation (Segmented Address):– CS:IP– DS:SI– ES:DI– SS:BP– SS:SP00000hFFFFFhfragmentation4Memory Storage Organization• Organized as SEGMENTS– Maximum segment size = 64KB– (Since 16 bit offsets: 216= 65,535 = 64KB)• Maximum Memory Size:– 220= 1,048,576 = 1MB• Newer Processors (386+) Can Utilize More Memory– Wider Address Registers 32 bits– 232= 4,294,967,296 = 4GBSegmented Memory ExampleCSESSSDSDataSegmentStackSegmentExtraSegmentCodeSegmentSegmentRegistersSystemMemory• Logical, Segmented Address:0FE6:012Bh• Offset, Index Address:012Bh• Physical Address:0FE60h → 65120+ 012Bh → 299 0FF8Bh → 6514900000hFFFFFhSegment Locations in Physical Memorysegment a segment bsegment csegment dsegment e0h10000h 20000h30000hcontiguouspartially overlappedfully overlappedLogicalSegmentsPhysicalMemoryNote that segments can overlap. This means that two different logical addresses can refer to the same physical address (aliasing).5Segmented Memory Aliasing• Logical, Segmented Address 1:DS:SI = 1234:4321• Physical Address:12340h → 74560+ 4321h → 1718516661h → 91745• Logical, Segmented Address 2:ES:DI = 1665:0011• Physical Address:16650h → 91728+ 0011h → 0001716661h → 91745Memory Data Organization• 1 Word = 16 bits• Byte Addressable•Little Endian Arrangement– MSB (Most Significant Byte) at Higher Address0727H0726H0725H0724H0723H0722H072CH072BH072AH0729H0728H• Segment Address = ACEDHAD5F4HAD5F3HAD5F2HAD5FCHAD5FBHAD5FAHAD5F9HAD5F8HAD5F7HAD5F6HAD5F5H• Logical Address = 0724H• Physical Address = ACED0H + 0724H= AD5F4H• M[ACED:0724]= M[AD5F4] (word read)= 5502H02H18HA3H7EH69HAAH2EH00H55H11H72H0H 2H 5H 5H01010101001000000724H 0725Hhexbinaryoffset or logicaladdressincreasingRegister Transfer Language• When describing memory/register operations, will use Register Transfer Language (RTL)rega ← regb transfer regb to rega (ax ← cx)rega ← reg a op reg b rega gets result of rega op regb rega ← M[location N] transfer contents of memory location Nto reg a (mem read operation)M[location N] ← rega transfer reg a to memory location N(write operation)Size of memory operation (byte, word, dword) depends on registersize or instruction.6Memory Read Operations0727H0726H0725H0724H0723H0722H072CH072BH072AH0729H0728HAD5F4HAD5F3HAD5F2HAD5FCHAD5FBHAD5FAHAD5F9HAD5F8HAD5F7HAD5F6HAD5F5H02H18HA3H7EH69HAAH2EH00H55H11H72Hoffset or logicaladdressincreasingByte Read:al ← M[0724h] after: al = 02hWord Read:ax ← M[0724h] after: ax = 5502hDword Readeax ← M[0724h] after: eax = 2E005502hMemory Write OperationsAssume EAX = FAC4237B hByte Write: M[0724h] ← al0727H0726H0725H0724H0723H0722H072CH072BH072AH0729H0728HAD5F4HAD5F3HAD5F2HAD5FCHAD5FBHAD5FAHAD5F9HAD5F8HAD5F7HAD5F6HAD5F5H02H18HA3H7EH69HAAH2EH00H55H11H72Hbefore:0727H0726H0725H0724H0723H0722H072CH072BH072AH0729H0728HAD5F4HAD5F3HAD5F2HAD5FCHAD5FBHAD5FAHAD5F9HAD5F8HAD5F7HAD5F6HAD5F5H7BH18HA3H7EH69HAAH2EH00H55H11H72Hafter:Memory Write Operations (cont.)Assume EAX = FAC4237B hWord Write: M[0724h] ← ax0727H0726H0725H0724H0723H0722H072CH072BH072AH0729H0728HAD5F4HAD5F3HAD5F2HAD5FCHAD5FBHAD5FAHAD5F9HAD5F8HAD5F7HAD5F6HAD5F5H02H18HA3H7EH69HAAH2EH00H55H11H72Hbefore:0727H0726H0725H0724H0723H0722H072CH072BH072AH0729H0728HAD5F4HAD5F3HAD5F2HAD5FCHAD5FBHAD5FAHAD5F9HAD5F8HAD5F7HAD5F6HAD5F5H7BH18HA3H7EH69HAAH2EH00H23H11H72Hafter:7Memory Write Operations (cont.)Assume EAX = FAC4237B hDWord Write: M[0724h] ←
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