1CS231: Computer Architecture IFriday, April 4, 2008CS 231 Review, April 4, 20082Announcements•Midterm Exam 2–Monday, April 7, 2008–151 Everitt Lab–7:00 – 9:00 pm–Bring your Ids–Covers lectures from (and including) Feb 25 through Apr 2–Familiarity with Midterm1 material will be assumed–Will have Reference sheet containing FlipFlop Characteristic and Excitation tables, as well as Boolean Algebra axioms•Midterm2 Optional Review Session–Monday during normal class time•HW8 Due Monday, April 14–One week after Midterm2–Covers lectures from Mar 31, Apr 2 and Apr 9CS 231 Review, April 4, 20083RAM: Static Memory •RAM–Size–Reading–Writing–Making “Longer” and “Wider” Memories•Three State BuffersCS 231 Review, April 4, 20084Random access memory•Sequential circuits all depend upon the presence of memory.–A flip-flop can store one bit of information.–A register can store a single “word,” typically 32-64 bits.•Random access memory, or RAM, allows us to store even larger amounts of data. Today we’ll see:–The basic interface to memory.–How you can implement static RAM chips hierarchically.•This is the last piece we need to put together a computer!CS 231 Review, April 4, 20085Introduction to RAM•Random-access memory, or RAM, provides large quantities of temporary storage in a computer system.•Remember the basic capabilities of a memory: –It should be able to store a value.–You should be able to read the value that was saved.–You should be able to change the stored value.•A RAM is similar, except that it can store manyvalues.–An address will specify which memory value we’re interested in.–Each value can be a multiple-bit word (e.g., 32 bits).•We’ll refine the memory properties as follows:A RAM should be able to:- Store many words, one per address- Read the word that was saved at a particular address- Change the word that’s saved at a particular addressCS 231 Review, April 4, 20086Block diagram of RAM•This block diagram introduces the main interface to RAM. –A Chip Select, CS, enables or disables the RAM.–ADRS specifies the address or location to read from or write to.–WR selects between reading from or writing to the memory.To read from memory, WR should be set to 0.OUT will be the n-bit value stored at ADRS.To write to memory, we set WR = 1.DATA is the n-bit value to save in memory.•This interface makes it easy to combine RAMs together, as we’ll see.2kx n memoryADRS OUTDATACSWRknnCS WR Memory operation0 x None1 0 Read selected word1 1 Write selected wordCS 231 Review, April 4, 20087Memory sizes•We refer to this as a 2kx n memory.–There are k address lines, which can specify one of 2kaddresses.–Each address contains an n-bit word.•For example, a 224x 16 RAM contains 224= 16M words, each 16 bits long.–The RAM would need 24 address lines.–The total storage capacity is 224x 16 = 228bits.2kx n memoryADRS OUTDATACSWRknnCS 231 Review, April 4, 20088Reading RAM•To readfrom this RAM, the controlling circuit must:–Enable the chip by ensuring CS = 1.–Select the read operation, by setting WR = 0.–Send the desired address to the ADRS input.–The contents of that address appear on OUT after a little while.•Notice that the DATA input is unused for read operations.2kx n memoryADRS OUTDATACSWRknnCS 231 Review, April 4, 20089Writing RAM•To writeto this RAM, you need to:–Enable the chip by setting CS = 1.–Select the write operation, by setting WR = 1.–Send the desired address to the ADRS input.–Send the word to store to the DATA input.•The output OUT is not needed for memory write operations.2kx n memoryADRS OUTDATACSWRknnCS 231 Review, April 4, 200810Starting with latches•To start, we can use one latch to store each bit. A one-bit RAM cell is shown here.•Since this is just a one-bit memory, an ADRS input is not needed.•Writing to the RAM cell:–When CS = 1 and WR = 1, the latch control input will be 1.–The DATA input is thus saved in the D latch.•Reading from the RAM cell and maintaining the current contents:–When CS = 0 or when WR = 0, the latch control input is also 0, so the latch just maintains its present state.–The current latch contents will appear on OUT.CS 231 Review, April 4, 200811My first RAM•We can use these cells to make a 4 x 1 RAM. •Since there are four words, ADRS is two bits.•Each word is only one bit, so DATA and OUT are one bit each.•Word selection is done with a decoder attached to the CS inputs of the RAM cells. Only one cell can be read or written at a time.•Notice that the outputs are connected together with a singleline!CS 231 Review, April 4, 200812•In normal practice, it’s bad to connect outputs together. If the outputs have different values, then a conflict arises.•The standard way to “combine” outputs is to use OR gates or muxes.•This can get expensive, with many wires and gates with large fan-ins.Connecting outputs togetherThe “C” in LogicWorks means “conflict.”CS 231 Review, April 4, 200813Those funny triangles•The triangle represents a three-state buffer.•Unlike regular logic gates, the output can be one of threedifferent possibilities, as shown in the table.•“Disconnected” means no output appears at all, in which case it’s safe to connect OUT to another output signal.•The disconnected value is also sometimes called high impedance or Hi-Z.EN IN OUT 0 x Disconnected 1 0 0 1 1 1CS 231 Review, April 4, 200814Connecting three-state buffers together•You can connect several three-state buffer outputs together if you can guaranteethat only one of them is enabled at any time.•The easiest way to do this is to use a decoder!•If the decoder is disabled, then all the three-state buffers will appear to be disconnected, and OUT will also appear disconnected.•If the decoder is enabled, then exactly one of its outputs will be true, so only one of the tri-state buffers will be connected and produce an output.•The net result is we can save some wire and gate costs. We also get a little more flexibility in putting circuits together.CS 231 Review, April 4, 200815Bigger and better•Here is the 4 x 1 RAM once again.•How can we make a “wider” memory with more bits per word, like maybe a 4 x 4 RAM?•Duplicate the stuff in the blue box!CS 231 Review, April 4, 200816A 4 x 4 RAM•DATA and OUT are now each fourbits long, so you can read and write four-bit words.CS 231 Review, April
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