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U of I CS 231 - Instruction Encoding

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1CS231: Computer Architecture IFriday, April 27, 2007-Instruction Encoding- &-Control Unit-CS 231 Review, April 27, 20072Instruction encoding• We’ve already seen some important aspects of processor design.– A datapath contains an ALU, registers and memory.– Programmers and compilers use instruction sets to issue commands.• Now let’s complete our processor with a control unit that convertsassembly language instructions into datapath signals.– Today we’ll see how control units fit into the big picture, and howassembly instructions can be represented in a binary format.– On Wednesday we’ll show all of the implementation details for oursample datapath and assembly language.CS 231 Review, April 27, 20073Review: Datapath• Recall that our ALU hasdirect access only to theregister file.• RAM contents must becopied to the registersbefore they can be used asALU operands.• Similarly, ALU results mustgo through the registersbefore they can be storedinto memory.• We rely on data movementinstructions to transfer databetween the RAM and theregister file.D data Write D address A address B addressA data B dataRegister FileWRDAAA BAQ D1 D0 S RAM ADRS DATA CS WROUTMW+5VA BALUFZNCVFSFS MDS D1 D0 Q Constant MBCS 231 Review, April 27, 20074Block diagram of a processor• The control unit connects programs with the datapath.– It converts program instructions into control words for thedatapath, including signals WR, DA, AA, BA, MB, FS, MW, MD.– It executes program instructions in the correct sequence.– It generates the “constant” input for the datapath.• The datapath also sends information back to the control unit. Forinstance, the ALU status bits V, C, N, Z can be inspected by branchinstructions to alter a program’s control flow.ControlUnitDatapathControl signalsStatus signalsProgramCS 231 Review, April 27, 20075A specific instruction set• The first thing we must do is agree upon an instruction set.• For our example CPU let’s stick with the three-address, register-to-register instruction set architecture introduced in the last lecture.– Data manipulation instructions have one destination and up to twosources, which must be either registers or constants.– We include dedicated load and store instructions to transfer datato and from memory.• Next week, we’ll learn about different kinds of instruction sets.CS 231 Review, April 27, 20076From assembly to machine language• Next, we must define a machine language, or a binary representation ofthe assembly instructions that our processor supports.• Our CPU includes three types of instructions, which have differentoperands and will need different representations.– Register format instructions require two source registers.– Immediate format instructions have one source register and oneconstant operand.– Jump and branch format instructions need one source register andone constant address.• Even though there are three different instruction formats, it is best tomake their binary representations as similar as possible.– This will make the control unit hardware simpler.– We’ll start by making all of our instructions 16 bits long.CS 231 Review, April 27, 20077Register format• An example register-format instruction:ADD R1, R2, R3• Our binary representation for these instructions will include:– A 7-bit opcode field, specifying the operation (e.g., ADD).– A 3-bit destination register, DR.– Two 3-bit source registers, SA and SB.OpcodeDestinationRegister(DR)SourceRegister A(SA)SourceRegister B(SB)15 9 8 6 5 3 2 0CS 231 Review, April 27, 20078Immediate format• An example immediate-format instruction:ADD R1, R2, #3• Immediate-format instructions will consist of:– A 7-bit instruction opcode.– A 3-bit destination register, DR.– A 3-bit source register, SA.– A 3-bit constant operand, OP.OpcodeDestinationRegister(DR)SourceRegister A(SA)Operand(OP)15 9 8 6 5 3 2 0CS 231 Review, April 27, 20079Jump and branch format• Two example jump and branch instructions:BZ R3, -24JMP 18• Jump and branch format instructions include:– A 7-bit instruction opcode.– A 3-bit source register SA for branch conditions.– A 6-bit address field, AD, for storing jump or branch offsets.• Our branch instructions support only one source register. Other typesof branches can be simulated from these basic ones.OpcodeAddressBits 5-3(AD)SourceRegister A(SA)AddressBits 2-0(AD)15 9 8 6 5 3 2 0CS 231 Review, April 27, 200710Organizing our instructions• How can we select binary opcodes for each possible operation?– In general, “similar” instructions should have similar opcodes. Again,this will lead to simpler control unit hardware.– We can divide our instructions into eight different categories, eachof which require similar datapath control signals.• To show the similarities within categories, we’ll look at register-basedALU operations and memory write operations in detail.Instruction typeRegister-format ALU operationRegister-format shift operationMemory write (from registers)Memory read (to registers)Immediate ALU operationImmediate shift operationConditional branchJumpCS 231 Review, April 27, 200711Register format ALU operationsADD R1, R2, R3• All register format ALUoperations need the samevalues for the followingcontrol signals:• MB = 0, because all operandscome from the register file.• MD = 0 and WR = 1, to savethe ALU result back into aregister.• MW = 0 since RAM is notmodified.DRegister fileA B DAAABAA BALUGFSVCNZ1 0Mux BMB 00 1Mux DMD 0ADRS DATAData RAMOUTMW 0constantWR 1CS 231 Review, April 27, 200712Memory write operationsST (R0), R1• All memory write operationsneed the same values for thefollowing control signals:• MB = 0, because the data towrite comes from theregister file.• MD = X and WR = 0, sincenone of the registers arechanged.• MW = 1, to update RAM.DRegister fileA B DAAABAA BALUGFSVCNZ1 0Mux BMB 00 1Mux DMD X ADRS DATAData RAMOUTMW 1constantWR 0CS 231 Review, April 27, 200713Selecting opcodes• Instructions in each of these categories are similar, so it would beconvenient if those instructions had similar opcodes.• We’ll assign opcodes so that all instructions in the same category willhave the same first three opcode bits (bits 15-13 of the instruction).• Next time we’ll talk about the other instruction categories shown here.Opcode bitsInstruction type 15 1413Register-format ALU


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U of I CS 231 - Instruction Encoding

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