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U of I CS 231 - Flip-Flops

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Flip-flops 1Flip-Flops• So, we’ve seen how latches can be used as memory in a circuit.• Latches introduce new problems:– We need to know when to enable a latch.– We also need to quickly disable a latch.– In other words, it’s difficult to control the timing of latches in a large circuit.• We solve these problems with two new elements: clocks and flip-flops– Clocks tell us when to write to our memory.– Flip-flops allow us to quickly write the memory at clearly defined times.– Used together, we can create circuits without worrying about thememory timing.Flip-flops 2An SR latch with a control input• Here is an SR latch with a control input C.• Notice the hierarchical design!– The dotted blue box is the S’R’ latch.– The additional NAND gates are simply used to generate the correct inputs for the S’R’ latch.• The control input acts just like an enable.C S R S’ R’ Q0 x x 1 1 No change1 0 0 1 1No change1 0 1 1 0 0 (reset)1 1 0 0 1 1 (set)1 1 1 0 0 Avoid!Flip-flops 3D latch• Finally, a D latch is based on an S’R’ latch. The additional gates generate the S’ and R’ signals, based on inputs D (“data”) and C (“control”).– When C = 0, S’ and R’ are both 1, so the state Q does not change.– When C = 1, the latch output Q will equal the input D.• No more messing with one input for set and another input for reset!• Also, this latch has no “bad” input combinations to avoid. Any of the four possible assignments to C and D are valid.C D Q0 xNo change1 0 01 1 1Flip-flops 4Using latches in real life• We can connect some latches, acting as memory, to an ALU.• Let’s say these latches contain some value that we want to increment.– The ALU should read the current latch value.– It applies the “G = X + 1” operation.– The incremented value is stored back into the latches.• At this point, we have to stop the cycle, so the latch value doesn’t get incremented again by accident.• One convenient way to break the loop is to disable the latches.+1ALUSXGLatchesDQCFlip-flops 5The problem with latches• The problem is exactly whento disable the latches. You have to wait long enough for the ALU to produce its output, but no longer.– But different ALU operations have different delays. For instance, arithmetic operations might go through an adder, whereas logicaloperations don’t.– Changing the ALU implementation, such as using a carry-lookahead adder instead of a ripple-carry adder, also affects the delay.• In general, it’s very difficult to know how long operations take, and how long latches should be enabled for.+1ALUSXGLatchesDQCFlip-flops 6Making latches work right• Our example used latches as memory for an ALU.– Let’s say there are four latches initially storing 0000.– We want to use an ALU to increment that value to 0001.• Normally the latches should be disabled, to prevent unwanted data from being accidentally stored.– In our example, the ALU can read the current latch contents, 0000, and compute their increment, 0001.– But the new value cannot be stored back while the latch is disabled. +1ALUSXGLatchesDQC000000001Flip-flops 7Writing to the latches• After the ALU has finished its increment operation, the latch can be enabled, and the updated value is stored. • The latch must be quickly disabled again, beforethe ALU has a chance to read the new value 0001 and produce a new result 0010.+1ALUSXGLatchesDQC100010001+1ALUSXGLatchesDQC000010010Flip-flops 8• So to use latches correctly within a circuit, we have to:– Keep the latches disabled until new values are ready to be stored.– Enable the latches just long enough for the update to occur.• There are two main issues we need to address: How do we know exactly when the new values are ready?We’ll add another signal to our circuit. When this newsignal becomes 1, the latches will know that the ALUcomputation has completed and data is ready to be stored. How can we enable and then quickly disable the latches?This can be done by combining latches together in aspecial way, to form what are called flip-flops.Two main issuesFlip-flops 9Clocks and synchronization• A clock is a special device that whose output continuously alternates between 0 and 1.• The time it takes the clock to change from 1 to 0 and back to 1 is called the clock period, or clock cycle time.• The clock frequency is the inverse of the clock period. The unit of measurement for frequency is the hertz.• Clocks are often used to synchronize circuits.– They generate a repeating, predictable pattern of 0s and 1s thatcan trigger certain events in a circuit, such as writing to a latch.– If several circuits share a common clock signal, they can coordinate their actions with respect to one another.• This is similar to how humans use real clocks for synchronization.clock periodFlip-flops 10More about clocks• Clocks are used extensively in computer architecture.• All processors run with an internal clock.– Modern chips run at frequencies up to 3.8 GHz.– This works out to a cycle time as little as 0.26 ns!• Memory modules are often rated by their clock speedstoo—examples include “PC133” and “DDR400” memory.• Be careful...higher frequencies do not always mean faster machines!– You also have to consider how much work is actually being done during each clock cycle.– How much stuff can really get done in just 0.26 ns?– Take CS232.Flip-flops 11Synchronizing our example• We can use a clock to synchronize our latches with the ALU.– The clock signal is connected to the latch control input C.– The clock controls the latches. When it becomes 1, the latches will be enabled for writing.• The clock period must be set appropriately for the ALU.– It should not be too short. Otherwise, the latches will start writing before the ALU operation has finished.– It should not be too long either. Otherwise, the ALU might produce a new result that will accidentally get stored, as we saw before.• The faster the ALU runs, the shorter the clock period can be.+1ALUSXGLatchesDQCFlip-flops 12• The second issue was how to enable a latch for just an instant.• Here is the internal structure of a D flip-flop.– The flip-flop inputs are C and D, and the outputs are Q and Q’.– The D latch on the left is the master, while the SR latch on the right is called the slave.• Note the layout here.– The flip-flop input D is connected directly to the master


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U of I CS 231 - Flip-Flops

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