EE178 Lecture Module 2Lecture #4 AgendaImplementation TechnologiesSlide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Lecture #5 AgendaSlide 21Slide 22Slide 23Slide 24Slide 25Field Programmable Gate ArraysSlide 27Slide 28Slide 29Lecture #6 AgendaXilinx Spartan-3 FamilySlide 32Spartan-3 Product MatrixChoice of PackagesSlide 35IOB ElementI/O Block AdvantagesComprehensive ConnectivitySelectIOSelectIO StandardsSelectIO Output BanksSelectIO Input BanksI/O Signal TypesSingle Ended I/ODifferential I/ODifferential I/O BenefitsDigitally Controlled Impedance DriversSignal Integrity AdjustmentSystem Interface SummarySlide 50Digital Clock Manager (DCM)DCM Functional BlocksDelay Locked Loop (DLL)DLL Functional BlocksDLL: Adjust I/O TimingDLL: Phase ShiftDLL: Clock MirrorsDLL: Frequency AdjustmentDigital Phase Shifter (DPS)Digital Frequency Synthesizer (DFS)DCM Clock OptionsClock Management SummaryLecture #7 AgendaSlide 64Configurable Logic Block (CLB)Spartan-3 Slice CapabilitiesSlide 67Four-Input LUTDedicated MultiplexersDistributed RAMShift RegisterArithmetic / Carry LogicEmbedded MultipliersSpartan-3 CLB SummarySlide 75BlockRAMSlide 77True Dual-PortDual-Port FlexibilityEmbedded Memory SummarySlide 81Routing Wire TypesGlobal RoutingRouting SummaryEE178 LectureModule 2Eric CrabillSJSU / XilinxFall 2005Lecture #4 Agenda•Survey of implementation technologies.Implementation Technologies•Small scale and medium scale integration.–Up to about 200 gates per device–Most common is 74xx type devices•Gates, flip flops, latches.•Decoders, registers, counters, andother functional building blocks.Implementation Technologies•Large scale integration.–Ranging from 200 to 200,000 gates per device.–Small memories, programmable logic devices,custom designs.•Very large scale integration.–Above 200,000 gates per device.–Often “gate count” is replaced bytransistor count because these largedesigns have integrated memories, etc.Implementation Technologies•Survey of small and medium scalecomponents by browsing data books.–Different functional classes.–Generally used as “glue” logic now,to help interface larger scale components.–Back in the day, large designs were doneusing this technology.Implementation Technologies•Advantages of small and medium scale,particularly with regard to 74xx stuff.–Easy to understand functions.–Exceptional signal visibility.•Disadvantages.–Low logic density means big boardsor small designs only.–Higher power consumption.–Cost per function, failure concerns.Implementation Technologies•Survey of large scale components, forlogic design, particularly programmablelogic devices in this density.–Many different flavors of devices; mostdraw on basic device types.•ROM, PLA, PAL = PLDs.•CPLDs–Can be used as glue logic but have enoughavailable logic to implement significantdesigns in larger parts.Implementation Technologies•Advantages of large scale integration.–Higher logic density means smaller boardsor larger designs.–Many devices can be programmed andreprogrammed, saving expense whenchanges are made.•Disadvantages.–Need to learn how to use and program.–Signal visibility is reduced.Implementation Technologies•What is a ROM? How can I use it?•What is a PLA? How can I use it?•What is a PAL? How can I use it?•How are all these things related?•What, then, is a CPLD?2N x MROMN inputs M outputsImplementation Technologies•A ROM is a SOP logic devicewith a fixed AND array anda programmable OR array.•You can implement M functionsof N inputs in this ROM.Implementation Technologies•You basically specify a truth table ofthe functions when you program the ROM.•There is no advantage to simplifying thefunction when you are using a ROM sinceyou need to specify the entire list ofminterms anyway…N1N0M0M1Fixed ConnectionProgrammable ConnectionImplementation Technologies•ROM of 2^N by M; N = 2, M=2•M0 = N1•N0 + N1•N0’•M1 = N1•N0 + N1’ •N0’PLAN inputs M outputsImplementation Technologies•A PLA is a SOP logic device with aprogrammable AND array (fewer pt’s thana ROM) and a programmable OR array.•You can implement functions using theavailable minterms, which may be sharedbetween functions.Implementation Technologies•You have to reduce your design to asum of products which will hopefullybe realizable with the available minterms.•Computer aided design tools are availableto do optimization for product term sharing.N1N0M0M1Fixed ConnectionProgrammable ConnectionImplementation Technologies•PLA of N inputs and M out; N = 2, M=2•M0 = N1•N0 + N1•N0’•M1 = N1•N0 + N1’ •N0’PALN inputs M outputsImplementation Technologies•A PAL is a SOP logic devicewith a programmable AND arrayand a fixed OR array.•You can implement functions usingthe available minterms for each outputfunction (no pt sharing).Implementation Technologies•Again, the design has to be reduced if possible.•No product term sharing, and note thatin real devices, each output functionmay have access to a different numberof product terms.N1N0M0M1Fixed ConnectionProgrammable ConnectionImplementation Technologies•PAL of N inputs and M out; N = 2, M=2•M0 = N1•N0 + N1•N0’•M1 = N1•N0 + N1’ •N0’ insufficient mintermsImplementation Technologies•A CPLD is a complex programmablelogic device that essentially consistsof a number of programmable logicblocks (such as a PLA, PAL, andless commonly, ROM) connected bya programmable interconnect array.•Why has CPLD density stagnated?Lecture #5 Agenda•Survey of implementation technologies.Implementation Technologies•Full Custom Logic.•Standard Cell Design.•Gate Array Design.•Field Programmable Logic.Implementation Technologies•Full Custom Logic.–Each primitive logic function or transistoris manually designed and optimized.–Most compact chip design, highestpossible speed, lowest power consumption.–Non recurring engineering cost (NRE) isthe highest for obvious reasons.–Rarely used today due to high engineeringcost and low productivity; polygon pushing.Implementation Technologies•Standard Cell Design.–Predefined logic blocks (a la 74xx style)are made available to the designer in acell library; the design is built with these.–Done with schematic capture or HDL.–Automated tools place and route the cells.–Cells are often standard dimensions tofacilitate automated place and
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