Control units•Control Unit 1•In the last lecture, we introduced the basic structure of a control unit, and translated our assembly instructions into a binary representation.• Today we fill in the last piece of the processor and build a control unitto convert these binary instructions into datapath signals.• At the end of the lecture, we’ll have a complete example processor!Datapath reviewDRegister fileA BWRDAAABAABFS1 0Mux BMBADRSDATAconstant• Set WR = 1 to write one of the registers.• DA is the register to save to.• AA and BA select the source registers.• MB chooses a register or a constant operand.• FS selects an ALU operation.•MW = 1 to write to memory.Control Unit 2ABALUGFSVCNZ0 1Mux DMDADRSDATAData RAMOUTMW•MW = 1 to write to memory.• MD selects between the ALU result and the RAM output.• V, C, N and Z are status bits.Instruction format review• We have three different instruction formats, each 16 bits long with a seven-bit opcode and nine bits for source registers or constants.• The first three bits of the opcode determine the instruction category, while the other four bits indicate the exact instruction.– For ALU/shift instructions, the four bits choose an ALU operation.– For branches, the bits select one of eight branch conditions.– We only support one one load, one store and one jump instruction.Control Unit 315 9 8 6 5 3 2 0OpcodeDestination (DR) orAddress 5-3 (AD)Register A (SA)Register B (SB),Operand (OP), orAddress 2-0 (AD)Block diagram of a processor• The control unit connects programs with the datapath.–It converts program instructions into control wordsfor the datapath, including signals WR, DA, AA, BA, MB, FS, MW, MD.ControlUnitDatapathControl signalsStatus signalsProgramControl Unit 4–It converts program instructions into control wordsfor the datapath, including signals WR, DA, AA, BA, MB, FS, MW, MD.– It executes program instructions in the correct sequence.– It generates the “constant” input for the datapath.• The datapath also sends information back to the control unit. For instance, the ALU status bits V, C, N, Z can be inspected by branch instructions to alter a program’s control flow.Where does the program go?• We’ll use a Harvard architecture, which includes two memory units.– An instruction memory holds the program.– A separate data memory is used for computations.– The advantage is that we can read an instruction andload or store data in the same clock cycle.• For simplicity, our diagrams do not show any WR or DATA inputs to the instruction memory. ADRSControl Unit 5• Caches in modern CPUs often feature a Harvard architecture like this.• However, there is usually a single main memory that holds both program instructions and data, in a Von Neumann architecture.ADRSInstructionRAMOUTADRS DATAData RAMOUTMWProgram counter• A program counter or PC addresses the instruction memory, to keep track of the instruction currently being executed.• On each clock cycle, the counter does one of two things.– If Load = 0, the PC increments, so the next instruction in memory will be executed.– If Load = 1, the PC is updated with Data, which represents some address specified in a jump or branch instruction.DataControl Unit 6ADRSInstructionRAMOUTPCLoadDataInstruction decoder• The instruction decoder is a combinational circuit that takes a machine language instruction and produces the matching control signals for the datapath.• These signals tell the datapath which registers or memory locations to access, and what ALU operations to perform.ADRSInstructionRAMOUTPCLoadDataControl Unit 7(to the datapath)Instruction DecoderDA AA BA MB FS MD WR MWJumps and branches• Finally, the branch control unitdecides what the PC’s next value should be.– For jumps, the PC should be loaded with the target address specified in the instruction.– For branch instructions, the PC should be loaded with the target address only if the ADRSInstructionRAMOUTPCBranchControlVCNZControl Unit 8PC should be loaded with the target address only if the corresponding status bit is true.– For all other instructions, the PC should just increment.Instruction DecoderDA AA BA MB FS MD WR MWThat’s it!• This is the basic control unit. On each clock cycle:1. An instruction is read from the instruction memory.2. The instruction decoder generates the matching datapath control word.3. Datapath registers are read and sent to the ALU or the ADRSInstructionRAMOUTPCBranchControlVCNZControl Unit 9and sent to the ALU or the data memory.4. ALU or RAM outputs are written back to the register file.5. The PC is incremented, or reloaded for branches and jumps.Instruction DecoderDA AA BA MB FS MD WR MWThe whole processorDRegister fileA BWRDAAABA1 0Mux BMBconstantADRSInstructionRAMOUTPCBranchControlVCNZControl Unit DatapathControl Unit 10A BALUGFSVCNZ0 1Mux DMDADRS DATAData RAMOUTMWInstruction DecoderDA AA BA MB FS MD WR MWImplementing the instruction decoder• The first thing we’ll look at is how to build the instruction decoder.• The instruction decoder’s input is a 16-bit binary instruction I that comes from the instruction memory.• The decoder’s output is a control word for the datapath. This includes:– WR, DA, AA, BA, and MD signals to control the register file.ADRSInstructionRAMOUTInstruction DecoderControl Unit 11control the register file.– FS for the ALU operation.– MW for the data memory write enable.– MB for selecting the second operand.• We’ll see how these signals are generated for each of the three instruction formats.DA AA BA MB FS MD WR MWMB, MD, WR and MW• The following table shows the correct signals MB, MD, WR and MW for each of the eight different instruction categories we defined. Control signalsInstruction type MB MD WR MWRegister-format ALU operation 0 0 1 0Register-format shift operation 0 0 1 0Memory write (from registers) 0 X 0 1Memory read (to registers) X 1 1 0Immediate ALU operation1010Control Unit 12• As mentioned last time, this is the sense in which these categories contain “similar” instructions.Immediate ALU operation1010Immediate shift operation 1 0 1 0Conditional branch X X 0 0Jump X X 0 0Eight categories of instructionsControl signalsInstruction type MB MD WR MWRegister-format ALU operation 0 0 1 0Register-format shift operation 0 0 1 0Memory write (from registers) 0 X 0 1Memory read (to registers) X 1 1 0Immediate ALU
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