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U of I CS 231 - Instruction Encoding & Control Unit

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CS231: Computer Architecture IInstruction encodingReview: DatapathBlock diagram of a processorA specific instruction setFrom assembly to machine languageRegister formatImmediate formatJump and branch formatOrganizing our instructionsRegister format ALU operationsMemory write operationsSelecting opcodesALU and shift instructionsBranch instructionsSample opcodesSummaryControl unitsWhere does the program go?Program counterInstruction decoderJumps and branchesThat’s it!The whole processorSlide 251CS231: Computer Architecture IFriday, April 27, 2007-Instruction Encoding- & -Control Unit-CS 231 Review, April 27, 20072Instruction encoding•We’ve already seen some important aspects of processor design.–A datapath contains an ALU, registers and memory.–Programmers and compilers use instruction sets to issue commands.•Now let’s complete our processor with a control unit that converts assembly language instructions into datapath signals.–Today we’ll see how control units fit into the big picture, and how assembly instructions can be represented in a binary format.–On Wednesday we’ll show all of the implementation details for our sample datapath and assembly language.CS 231 Review, April 27, 20073Review: Datapath•Recall that our ALU has direct access only to the register file.•RAM contents must be copied to the registers before they can be used as ALU operands.•Similarly, ALU results must go through the registers before they can be stored into memory.•We rely on data movement instructions to transfer data between the RAM and the register file.D data Write D address A address B addressA data B dataRegister FileWRDAAA BAQ D1 D0 S RAM ADRS DATA CS WROUTMW+5VA BALUFZNCVFSFS MDS D1 D0 Q Constant MBCS 231 Review, April 27, 20074Block diagram of a processor•The control unit connects programs with the datapath.–It converts program instructions into control words for the datapath, including signals WR, DA, AA, BA, MB, FS, MW, MD.–It executes program instructions in the correct sequence.–It generates the “constant” input for the datapath.•The datapath also sends information back to the control unit. For instance, the ALU status bits V, C, N, Z can be inspected by branch instructions to alter a program’s control flow.ControlUnitDatapathControl signalsStatus signalsProgramCS 231 Review, April 27, 20075A specific instruction set•The first thing we must do is agree upon an instruction set.•For our example CPU let’s stick with the three-address, register-to-register instruction set architecture introduced in the last lecture.–Data manipulation instructions have one destination and up to two sources, which must be either registers or constants.–We include dedicated load and store instructions to transfer data to and from memory.•Next week, we’ll learn about different kinds of instruction sets.CS 231 Review, April 27, 20076From assembly to machine language•Next, we must define a machine language, or a binary representation of the assembly instructions that our processor supports.•Our CPU includes three types of instructions, which have different operands and will need different representations.–Register format instructions require two source registers.–Immediate format instructions have one source register and one constant operand.–Jump and branch format instructions need one source register and one constant address.•Even though there are three different instruction formats, it is best to make their binary representations as similar as possible.–This will make the control unit hardware simpler.–We’ll start by making all of our instructions 16 bits long.CS 231 Review, April 27, 20077Register format•An example register-format instruction:ADD R1, R2, R3•Our binary representation for these instructions will include:–A 7-bit opcode field, specifying the operation (e.g., ADD).–A 3-bit destination register, DR.–Two 3-bit source registers, SA and SB.OpcodeDestinationRegister(DR)SourceRegister A(SA)SourceRegister B(SB)15 9 8 6 5 3 2 0CS 231 Review, April 27, 20078Immediate format•An example immediate-format instruction:ADD R1, R2, #3•Immediate-format instructions will consist of:–A 7-bit instruction opcode.–A 3-bit destination register, DR.–A 3-bit source register, SA.–A 3-bit constant operand, OP.OpcodeDestinationRegister(DR)SourceRegister A(SA)Operand(OP)15 9 8 6 5 3 2 0CS 231 Review, April 27, 20079Jump and branch format•Two example jump and branch instructions:BZ R3, -24 JMP 18•Jump and branch format instructions include:–A 7-bit instruction opcode.–A 3-bit source register SA for branch conditions.–A 6-bit address field, AD, for storing jump or branch offsets.•Our branch instructions support only one source register. Other types of branches can be simulated from these basic ones.OpcodeAddressBits 5-3(AD)SourceRegister A(SA)AddressBits 2-0(AD)15 9 8 6 5 3 2 0CS 231 Review, April 27, 200710Organizing our instructions•How can we select binary opcodes for each possible operation?–In general, “similar” instructions should have similar opcodes. Again, this will lead to simpler control unit hardware.–We can divide our instructions into eight different categories, each of which require similar datapath control signals.•To show the similarities within categories, we’ll look at register-based ALU operations and memory write operations in detail.I nstruction typeRegister-f ormat ALU operationRegister-f ormat shif t operationMemory write (f rom registers)Memory read (to registers)I mmediate ALU operationI mmediate shif t operationConditional branchJ umpCS 231 Review, April 27, 200711Register format ALU operationsADD R1, R2, R3•All register format ALU operations need the same values for the following control signals:•MB = 0, because all operands come from the register file.•MD = 0 and WR = 1, to save the ALU result back into a register.•MW = 0 since RAM is not modified.DRegister fileA B DAAABAA BALUGFSVCNZ1 0Mux BMB 00 1Mux DMD 0ADRS DATAData RAMOUTMW 0constantWR 1CS 231 Review, April 27, 200712Memory write operationsST (R0), R1•All memory write operations need the same values for the following control signals:•MB = 0, because the data to write comes from the register file.•MD = X and WR = 0, since none of the registers are changed.•MW = 1, to update RAM.DRegister fileA B DAAABAA BALUGFSVCNZ1 0Mux BMB 00 1Mux DMD X


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U of I CS 231 - Instruction Encoding & Control Unit

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