CS231 (Spring 06) Review SessionOutlineBlock diagram of RAMMemory Sizes (I)Memory Sizes (II)Memory Sizes (III)Bigger RAM from smaller RAMsMaking a wider Memory(Quiz RAM) Question 3Slide 11Read-Only MemoryROM TableROM Setup23 x 3 ROM Example(Quiz ROM) Question 1(Quiz ROM) Question 3Slide 18Programmable Logic Arrays3 x 4 x 3 PLA ExampleRegular K-map minimizationPLA minimizationPowerPoint PresentationPLA QuestionSlide 25CS231 (Spring 06)Review SessionSangkyum KimMar 31, 2006OutlineRAMROMPLABlock diagram of RAM 2k x n memoryADRS OUTDATACSWRknnCS WR Memory operation0 x None1 0 Read selected word1 1 Write selected wordCS: Chip SelectEnables or disables the RAMWRSelects between reading from or writing to the memoryMemory Sizes (I)There are k address lines.Each address contains an n-bit word.For example, a 215 x 8 RAM# of address lines:Total storage capacity:# of words: 2k x n memoryADRS OUTDATACSWRknn15215 x 8 = 218 bits = 215 bytes215, each 8bits longMemory Sizes (II)There are k address lines.Each address contains an n-bit word.For example, a 215 x 8 ROM# of address lines:Total storage capacity:# of words: 2k x n memoryADRS OUTDATACSWRknn15215 x 8 = 218 bits = 215 bytes215, each 8bits long 2k x n ROMADRS OUTCSk nMemory Sizes (III)8816# of words:# of address lines: # of data lines: 16864K = 26 x 210 = 216Similarly, for 256K x 8 RAM# of words:# of address lines: # of data lines: 188256K = 28 x 210 = 218Bigger RAM from smaller RAMs64K = 26 x 210 = 216# of words:# of address lines: # of data lines: 16864K x 8 RAM256K x 8 RAM# of words:# of address lines: # of data lines: 188256K = 28 x 210 = 2188816Making a wider Memory64K = 26 x 210 = 216# of words:# of address lines: # of data lines: 16864K x 8 RAM64K x 16 RAM# of words:# of address lines: # of data lines: 161664K = 26 x 210 = 216168 88 8(Quiz RAM) Question 3We want to build a memory with 2-byte words and a capacity of 220 bits. How many 8K x 8 RAM chips are needed? How many address lines are needed for the memory? How many of these address lines are connected to the address inputs of the RAM chips? How many of these address lines will be used to select the appropriate RAM chip(s)? What size decoder is needed to build the memory? 220 / (8K*8) = 220-16 = 24 = 16log2 (220 / (2*8)) = 16log2 8K = 1316 – 13 = 33 – to – 8 decoderOutlineRAMROMPLARead-Only Memory 2k x n memoryADRS OUTDATACSWRknn 2k x n ROMADRS OUTCSk nYou can think of a ROM as a combinational circuit that takes an address as input, and produces some data as the output.You can’t store arbitrary data into a ROM, so the same address will always contain the same data.ROM TableAddressA2A1A0DataV2V1V0000 000001 100010 110011 100100 101101 000110 011111 011You can think of a ROM as a combinational circuit that takes an address as input, and produces some data as the output.A ROM table is basically just a truth table.The table shows what data is stored at each ROM address.You can generate that data combinationally, using the address as the input.ROM Setup 2k x n ROMADRS OUTCSk nAddressA2A1A0DataV2V1V0000 000001 100010 110011 100100 101101 000110 011111 011V2 = m(1,2,3,4) V1 = m(2,6,7) V0 = m(4,6,7)A2A1A023 x 3 ROM Example 2k x n ROMADRS OUTCSk n(Quiz ROM) Question 1A ROM is to be used to implement a binary multiplier that multiplies two unsigned 7-bit numbers. Specify the size of the ROM by giving the number of words and the number of bits per word. Number of words = Number of bits per word = 214 = 1638414(Quiz ROM) Question 3A 256 x 12 ROM is to be constructed using eight ROM chips with enable and a 3-to-8 decoder. What size ROM chips are needed? Number of words = Number of bits per word = 28 / 8 = 28-3 = 3212OutlineRAMROMPLAProgrammable Logic ArraysA programmable logic array, or PLA, makes the decoder part of the ROM “programmable” too. Instead of generating all minterms, you can choose which products (not necessarily minterms) to generate.V2V1V0A2A1A0InputsOutputsAND arrayOR array3 x 4 x 3 PLA ExampleV2V1V0V2V1V0A2A1A0A2A1A0Regular K-map minimizationY0 0 0 1X 0 0 1 1ZY0 0 0 0X 1 0 1 1ZV2V1V0Y0 1 1 1X 1 0 0 0ZV2= m(1,2,3,4)V1= m(2,6,7)V0= m(4,6,7)AddressA2A1A0DataV2V1V0000 000001 100010 110011 100100 101101 000110 011111 011PLA minimizationY0 0 0 0X 1 0 1 1ZY0 1 1 1X 1 0 0 0ZY0 0 0 1X 0 0 1 1ZV2 = xy’z’ + x’z + x’yz’ V1 = x’yz’ + xy V0 = xy’z’ + xyV2= m(1,2,3,4)V1= m(2,6,7)V0= m(4,6,7)V2V1V0xy’z’xyx’zx’yz’V2= m(1,2,3,4) = xy’z’ + x’z + x’yz’V1= m(2,6,7) = x’yz’ + xyV0= m(4,6,7) = xy’z’ + xyA2A1A0PLA QuestionSuppose you wish to use a PLA to implement the two functions f and g, where: f(x,y,z) = OR(m2,m4,m5,m7) g(x,y,z) = OR(m1,m7)What is the minimum number of product terms you will need? List the product terms: 4x'yz', xy', xyz, x'y'zTHANK
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