CS231 (Spring 07) Review SessionOutlineAdministrative InformationSlide 4Read-Only MemoryROM TableROM Setup23 x 3 ROM Example(Quiz ROM) Question 1(Quiz ROM) Question 3Slide 11Programmable Logic Arrays3 x 4 x 3 PLA ExampleRegular K-map minimizationPLA minimizationSlide 16PLA QuestionSlide 18What is Computer Architecture?Two Parts (1) – MicroarchitectureTwo Parts (2) – System ArchitectureWhat is after CS231?CPU DesignDatapath - OverviewDatapath - RegistersDatapath - CPUDatapath - Register ALUDatapath – all togetherSlide 29A Program’s Life (1) – High-level languageA Program’s Life (2) – Assembly languageA Program’s Life (3) – Machine languageInstruction Set - OverviewSlide 34Assembly InstructionsCompiling ExampleSlide 37CS231 (Spring 07)Review SessionSangkyum KimApril 20, 2007OutlineAdministrative InformationROMPLADatapathISAAdministrative InformationHW9Due: 4/23 Mon 5:00 pm, TA office(SC 0212)HW10Contains big LogicWorks ProblemFinal ExamTime: 5/9 Wed 7-10pmPlace: SC 1404Contents: AllOutlineAdministrative InformationROMPLADatapathISARead-Only Memory 2k x n memoryADRS OUTDATACSWRknn 2k x n ROMADRS OUTCSk nYou can think of a ROM as a combinational circuit that takes an address as input, and produces some data as the output.You can’t store arbitrary data into a ROM, so the same address will always contain the same data.ROM TableAddressA2A1A0DataV2V1V0000 000001 100010 110011 100100 101101 000110 011111 011You can think of a ROM as a combinational circuit that takes an address as input, and produces some data as the output.A ROM table is basically just a truth table.The table shows what data is stored at each ROM address.You can generate that data combinationally, using the address as the input.ROM Setup 2k x n ROMADRS OUTCSk nAddressA2A1A0DataV2V1V0000 000001 100010 110011 100100 101101 000110 011111 011V2 = m(1,2,3,4) V1 = m(2,6,7) V0 = m(4,6,7)A2A1A023 x 3 ROM Example 2k x n ROMADRS OUTCSk n(Quiz ROM) Question 1A ROM is to be used to implement a binary multiplier that multiplies two unsigned 7-bit numbers. Specify the size of the ROM by giving the number of words and the number of bits per word. Number of words = Number of bits per word = 214 = 1638414(Quiz ROM) Question 3A 256 x 12 ROM is to be constructed using eight ROM chips with enable and a 3-to-8 decoder. What size ROM chips are needed? Number of words = Number of bits per word = 28 / 8 = 28-3 = 3212OutlineAdministrative InformationROMPLADatapathISAProgrammable Logic ArraysA programmable logic array, or PLA, makes the decoder part of the ROM “programmable” too. Instead of generating all minterms, you can choose which products (not necessarily minterms) to generate.V2V1V0A2A1A0InputsOutputsAND arrayOR array3 x 4 x 3 PLA ExampleV2V1V0V2V1V0A2A1A0A2A1A0Regular K-map minimizationY0 0 0 1X 0 0 1 1ZY0 0 0 0X 1 0 1 1ZV2V1V0Y0 1 1 1X 1 0 0 0ZV2= m(1,2,3,4)V1= m(2,6,7)V0= m(4,6,7)AddressA2A1A0DataV2V1V0000 000001 100010 110011 100100 101101 000110 011111 011PLA minimizationY0 0 0 0X 1 0 1 1ZY0 1 1 1X 1 0 0 0ZY0 0 0 1X 0 0 1 1ZV2 = xy’z’ + x’z + x’yz’ V1 = x’yz’ + xy V0 = xy’z’ + xyV2= m(1,2,3,4)V1= m(2,6,7)V0= m(4,6,7)V2V1V0xy’z’xyx’zx’yz’V2= m(1,2,3,4) = xy’z’ + x’z + x’yz’V1= m(2,6,7) = x’yz’ + xyV0= m(4,6,7) = xy’z’ + xyA2A1A0PLA QuestionSuppose you wish to use a PLA to implement the two functions f and g, where: f(x,y,z) = OR(m2,m4,m5,m7) g(x,y,z) = OR(m1,m7)What is the minimum number of product terms you will need? List the product terms: 4x'yz', xy', xyz, x'y'zOutlineAdministrative InformationROMPLADatapathISAWhat is Computer Architecture?Computer Architecture is the science and art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals. Computer architecture is not about using computers to design buildings.-- http://www.cs.wisc.edu/~arch/www/Two Parts (1) – MicroarchitectureMicroarchitecture Consist of a set of microprocessor design techniques, including instruction set, microcode, pipelining, cache systems, etc.Two Parts (2) – System ArchitectureSystem architecture How to organize a chuck of hardware resources Spread from mobile computing, PC to mainframe Include microprocessor, memory, I/O, operating system, networking, distributed system, security, dependability and so forth.What is after CS231?CS231 Computer Architecture I Basic course on computer architecture CS232 Computer Architecture II Second-level course on Computer architecture (1) instruction set architecture (ISA), (2) pipelining, (3) memory hierarchy, (4) input/output hardware and software CS433 Computer System Organization (UG/G) A “must take” course on computer architecture cover ISA design, pipeline design, memory hierarchy and so forth CS533 Parallel Computer Architecture Theoretical aspects of parallel and pipeline computationCPU DesignCPU design is extremely complex, fortunately however, this course will only introduce some basic concepts. Datapath – how does the data flow in a CPU Instruction set – programmer’s language to a CPU Control unit – how does CPUs control the operations.Datapath - OverviewFundamentally, the processor is just moving data between registers, possibly with some ALU computations. Actually, within a CPU, the data may also flow through cache, which is a part of the memory. Temporarily forget about what you learned before in CS231 . How do these components work What are they doing?ALURegistersMemoryCPUDatapath - RegistersRegister is the fastest and smallest storage component in a computer. Register file contains several registers. Only one control bit - WR. Remember the notation of size 2k x n We can read two value from the register file at once and write one value to it at once Any operation happens only on the positive edge of the clock. If possible, try to know the inside of the register file.nnnk kkD dataWriteD addressA address B addressA data B data Register FileDWRDAAAAB BADatapath - CPUALU is a key component in a CPU. No address line for ALUs. Output some status bits. The function select FS has more than one bit.A BALUFZNCVFSnnnmDatapath - Register ALUR0 R1 + R3 This
View Full Document
Unlocking...