Addressing mode summaryIssues in design of ISAsNumber of operandsTwo-address instructionsOne-address instructionsThe ultimate: zero addressesStack architecture exampleData movement instructionsRegister-to-register architecturesMemory-to-memory architecturesRegister-to-memory architecturesSize and speedSummary01/13/19 Instruction encoding 1Addressing mode summaryMode Notation Register transf er equivalentI mmediateLD R1, #CONSTR1 CONSTDirectLD R1, CONSTR1 M[CONST]Register indirectLD R1, (R0)R1 M[R0]I ndexedLD R1, CONST(R0)R1 M[R0 + CONST]RelativeLD R1, $CONSTR1 M[PC + CONST]I ndirectLD R1, [CONST]R1 M[M[CONST]]01/13/19 Instruction encoding 2Issues in design of ISAs•Characterization of application programs–What are typical programs like–What mix of instructions (ALU, Branch, ..)•Size of instruction word•Length of program –Number of instructions–Number of bytes–Number of instructions needed to code the same program may be different depending on the ISA•Clock period–Needs to be long enough to do one cycle of instruction•Single cycle instruction or multi-cycle instruction–Multi-cycle instructions: (we are skipping this)•Hardwired control vs micro-programmed control •Pipelined instructions01/13/19 Instruction encoding 3Number of operands•Another way to classify instruction sets is according to the number of operands that each data manipulation instruction can have.•Our example instruction set had three-address instructions, because each one had up to three operands—two sources and one destination.•This provides the most flexibility, but it’s also possible to have fewer than three operands.ADD R0, R1, R2operationdestination sourcesoperandsR0 R1 + R2Register transfer instruction:01/13/19 Instruction encoding 4Two-address instructions•In a two-address instruction, the first operand serves as both the destination and one of the source registers.•Some other examples and the corresponding C code:ADD R3, #1 R3 R3 + 1 R3++;MUL R1, #5 R1 R1 * 5 R1 *= 5;NOT R1 R1 R1’ R1 = ~R1;ADD R0, R1operationdestinationand source 1source 2operandsR0 R0 + R1Register transfer instruction:01/13/19 Instruction encoding 5•Some computers, like this old Apple II, have one-address instructions.•The CPU has a special register called an accumulator, which implicitly serves as the destination and one of the sources.•Here is an example sequence which increments M[R0]:LD (R0) ACC M[R0]ADD #1 ACC ACC + 1ST (R0) M[R0] ACCOne-address instructionsADD R0operation sourceACC ACC + R0Register transfer instruction:01/13/19 Instruction encoding 6The ultimate: zero addresses•If the destination and sources are all implicit, then you don’t have to specify any operands at all!–For the ALU instructions•This is possible with processors that use a stack architecture. –HP calculators and their “reverse Polish notation” use a stack.–The Java Virtual Machine is also stack-based.•How can you do calculations with a stack?–Operands are pushed onto a stack. The most recently pushed element is at the “top” of the stack (TOS).–Operations use the topmost stack elements as their operands. Those values are then replaced with the operation’s result.01/13/19 Instruction encoding 7Stack architecture example•From left to right, here are three stack instructions, and what the stack looks like after each example instruction is executed.•This sequence of stack operations corresponds to one register transfer instruction:TOS R1 + R2R1… stuff 1 …… stuff 2 …R2R1… stuff 1 …… stuff 2 …R1 + R2… stuff 1 …… stuff 2 …(Top)(Bottom)PUSH R1 PUSH R2 ADD01/13/19 Instruction encoding 8Data movement instructions•Finally, the types of operands allowed in data manipulation instructions is another way of characterizing instruction sets.–So far, we’ve assumed that ALU operations can have only register and constant operands.–Many real instruction sets allow memory-based operands as well. •We’ll use the book’s example and illustrate how the following operation can be translated into some different assembly languages.X = (A + B)(C + D)•Assume that A, B, C, D and X are really memory addresses.01/13/19 Instruction encoding 9Register-to-register architectures•Our programs so far assume a register-to-register, or load/store, architecture, which matches our datapath from last week nicely.–Operands in data manipulation instructions must be registers.–Other instructions are needed to move data between memory and the register file.•With a register-to-register, three-address instruction set, we might translate X = (A + B)(C + D) into:LD R1, A R1 M[A] // Use direct addressingLD R2, B R2 M[B]ADD R3, R1, R2 R3 R1 + R2 // R3 = M[A] + M[B]LD R1, C R1 M[C]LD R2, D R2 M[D]ADD R1, R1, R2 R1 R1 + R2 // R1 = M[C] + M[D]MUL R1, R1, R3 R1 R1 * R3 // R1 has the resultST X, R1 M[X] R1 // Store that into M[X]01/13/19 Instruction encoding 10Memory-to-memory architectures•In memory-to-memory architectures, all data manipulation instructions use memory addresses as operands.•With a memory-to-memory, three-address instruction set, we might translate X = (A + B)(C + D) into simply:•How about with a two-address instruction set?ADD X, A, B M[X] M[A] + M[B]ADD T, C, D M[T] M[C] + M[D] // T is temporary storageMUL X, X, T M[X] M[X] * M[T]MOVE X, A M[X] M[A] // Copy M[A] to M[X] firstADD X, B M[X] M[X] + M[B] // Add M[B]MOVE T, C M[T] M[C] // Copy M[C] to M[T]ADD T, D M[T] M[T] + M[D] // Add M[D]MUL X, T M[X] M[X] * M[T] // Multiply01/13/19 Instruction encoding 11Register-to-memory architectures•Finally, register-to-memory architectures let the data manipulation instructions access both registers and memory.•With two-address instructions, we might do the following:LD R1, A R1 M[A] // Load M[A] into R1 firstADD R1, B R1 R1 + M[B] // Add M[B]LD R2, C R2 M[C] // Load M[C] into R2ADD R2, D R2 R2 + M[D] // Add M[D]MUL R1, R2 R1 R1 * R2 // MultiplyST X, R1 M[X] R1 // Store01/13/19 Instruction encoding 12Size and speed•There are lots of tradeoffs in deciding how many and what kind of operands and addressing modes to support in a processor.•These decisions can affect the size of machine language programs.–Memory addresses are long compared to register file addresses, so instructions with memory-based
View Full Document
Unlocking...