Instruction encodingBlock diagram of a processorA specific instruction setFrom assembly to machine languageRegister formatImmediate formatPC-relative jumps and branchesJump and branch formatThe address field ADInstruction format uniformityInstruction formats and the datapathOrganizing our instructionsRegister format ALU operationsMemory write operationsSelecting opcodesALU and shift instructionsBranch instructionsSample opcodesSample instructionsWhere does the program go?Program counterInstruction decoderJumps and branchesThat’s it!The whole processorSummaryNext: Implementing the instruction decoder and the Branch Unit01/13/19 Instruction encoding 1Instruction encoding•We’ve already seen some important aspects of processor design.–A datapath contains an ALU, registers and memory.–Programmers and compilers use instruction sets to issue commands.•Now let’s complete our processor with a control unit that converts assembly language instructions into datapath signals.–Today we’ll see how control units fit into the big picture, and how assembly instructions can be represented in a binary format.01/13/19 Instruction encoding 2Block diagram of a processor•The control unit connects programs with the datapath.–It converts program instructions into control words for the datapath, including signals WR, DA, AA, BA, MB, FS, MW, MD.–It executes program instructions in the correct sequence.–It generates the “constant” input for the datapath.•The datapath also sends information back to the control unit. For instance, the ALU status bits V, C, N, Z can be inspected by branch instructions to alter a program’s control flow.ControlUnitDatapathControl signalsStatus signalsProgram01/13/19 Instruction encoding 3A specific instruction set•The first thing we must do is agree upon an instruction set.•For our example CPU let’s stick with the three-address, register-to-register instruction set architecture introduced in the last lecture.–Data manipulation instructions have one destination and up to two sources, which must be either registers or constants.–We include dedicated load and store instructions to transfer data to and from memory.•Later, we’ll learn about different kinds of instruction sets.01/13/19 Instruction encoding 4From assembly to machine language•Next, we must define a machine language, or a binary representation of the assembly instructions that our processor supports.•Our CPU includes three types of instructions, which have different operands and will need different representations.–Register format instructions require two source registers.–Immediate format instructions have one source register and one constant operand.–Jump and branch format instructions need one source register and one constant address.•Even though there are three different instruction formats, it is best to make their binary representations as similar as possible.–This will make the control unit hardware simpler.–We’ll start by making all of our instructions 16 bits long.01/13/19 Instruction encoding 5Register format•An instruction involving registers only is encoded in this format•An example register-format instruction:ADD R1, R2, R3•Our binary representation for these instructions will include:–A 7-bit opcode field, specifying the operation (e.g., ADD).–A 3-bit destination register, DR.–Two 3-bit source registers, SA and SB.OpcodeDestinationRegister(DR)SourceRegister A(SA)SourceRegister B(SB)15 9 8 6 5 3 2 001/13/19 Instruction encoding 6Immediate format•An example immediate-format instruction:ADD R1, R2, #3•Immediate-format instructions will consist of:–A 7-bit instruction opcode.–A 3-bit destination register, DR.–A 3-bit source register, SA.–A 3-bit constant operand, OP.OpcodeDestinationRegister(DR)SourceRegister A(SA)Operand(OP)15 9 8 6 5 3 2 001/13/19 Instruction encoding 7•We will use PC-relative addressing for jumps and branches, where the operand specifies the number of addresses to jump or branch from the current instruction.•We can assume each instruction occupies one word of memory.•The operand is a signed number.–It’s possible to jump or branch either “forwards” or “backwards.” –Backward jumps are often used to implement loops; see some of the examples from last week.LD R1, #10 1000 LD R1, #10LD R2, #3 1001 LD R2, #3JMP L 1002 JMP 2K LD R1, #20 1003 LD R1, #20LD R2, #4 1004 LD R2, #4L ADD R3, R3, R2 1005 ADD R3, R3, R2ST (R1), R3 1006 ST (R1), R3PC-relative jumps and branches01/13/19 Instruction encoding 8Jump and branch format•Two example jump and branch instructions:BZ R3, -24 JMP 18•Jump and branch format instructions include:–A 7-bit instruction opcode.–A 3-bit source register SA for branch conditions.–A 6-bit address field, AD, for storing jump or branch offsets.•Our branch instructions support only one source register. Other types of branches can be simulated from these basic ones.OpcodeAddressBits 5-3(AD)SourceRegister A(SA)AddressBits 2-0(AD)15 9 8 6 5 3 2 001/13/19 Instruction encoding 9The address field AD•AD is treated as a six-bit signed number, so you can branch up to 31 addresses forward (25-1), or up to 32 addresses backward (-25).•The address field is split into two parts for uniformity, so the SA field occupies the same position in all three instruction formats.OpcodeAddressBits 5-3(AD)SourceRegister A(SA)AddressBits 2-0(AD)15 9 8 6 5 3 2 001/13/19 Instruction encoding 10Instruction format uniformity•Notice the similarities between the different instruction formats.–The Opcode field always appears in the same position (bits 15-9).–DR is in the same place for register and immediate instructions.–The SA field also appears in the same position, even though this forced us to split AD into two parts for jumps and branches.•Tomorrow we’ll see how this leads to a simpler control unit.OpcodeDestinationRegister(DR)SourceRegister A(SA)SourceRegister B(SB)15 9 8 6 5 3 2 0OpcodeDestinationRegister(DR)SourceRegister A(SA)Operand(OP)OpcodeAddressBits 5-3(AD)SourceRegister A(SA)AddressBits 2-0(AD)01/13/19 Instruction encoding 11Instruction formats and the datapath•The instruction format and datapath are inter-related.–Since register addresses (DR, SA and SB) are three bits each, this instruction set can only support eight registers.–The constant operand (OP) is also three bits long. Its value will have to be sign-extended if the ALU supports wider inputs
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