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U of I CS 231 - Instruction set architectures

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04/26/05 ISA 1Instruction set architectures•Last week we built a simple, but complete, datapath.•The datapath is ultimately controlled by a programmer, so todaywe’ll look at several aspects of programming in more detail .–How programs are executed on processors–An i ntroduction to instruction set architectures–Example instructions and prog rams•Next, we’ll see how programs are encoded in a processor. Followingthat, we’ll finish our processor by designing a control unit, whichconverts our programs into signals for the datapath.04/26/05 ISA 2Progra mming and CPUs•Programs written i n a high-levellanguage like C++ must becompiled to produce an executableprogram.•The result is a CP U -specificmachine language program. Thiscan be loaded into memory andexecuted by the processor.•CS231 focuses on stuff below thedotted blue line, but ma ch inelanguage serves as the interfacebetween hardware and software.DatapathHigh-level prog ramExecutable fileControl wordsCompilerControl UnitHardwareSoftware04/26/05 ISA 3High-level languages•High-level l anguages pr ovide many useful programming constructs.–For, wh ile, and do loops–If-then-else state ments–Functions and procedures for code abstraction–Variables an d arrays for storage•Many languages prov ide safety features as well.–Static and dynamic typechecking–Garbage collection•High-level l anguages are also relatively portable.Theoretically, youcan write one program and compile it on many different processors.•It may be hard to understand what’s so “high-level” here, until youcompare these languages with...04/26/05 ISA 4Low-level languages•Each CPU has its ow n low-level instruction set, or machine language,which closely r eflects the CPU’s design.•Unfortunately, this means instruction sets are not easy for humansto work with!–Control flow is limited to “jump” and “branch” instructions, whichyou must use to make your own loops and conditionals.–Support for functions a nd procedures may be limited.–Memory addresses must be explicitly specified. You can’t justdeclare new variables and use them!–Very li ttle error checking is provided.–It’s difficult to convert machine languag e programs to differentprocessors.•Later we’ll look at some rough translations from C to machinelanguage.04/26/05 ISA 5Compiling•Processors can’t ex ecute programs written in high-level languagesdirectly, so a special program called a compiler is needed totranslate high-level programs into low-le vel machine code.•In the “good” old days, people often wrote machine languageprograms by hand to make their programs faster, smaller, or both.•Now, compilers almost always do a better job than peopl e.–Programs are becoming more complex, and it’s hard for humansto write and maintain large, effi cient machine language code.–CPUs a re becoming mor e complex. It’s d ifficult to write code thattakes full advantage of a processor’s features.•Some languages, like Perl or Lisp, are usually interpreted instead ofcompiled.–Programs are translated into an intermediate format.–This is a “middle ground” between efficiency and por tability.04/26/05 ISA 6Assembly and machine languages•Machine language instructions are sequences of bits in a specificorder.•To mak e things simpler, people typica lly u se assembly language.–We assign “mnemonic” names to ope rations and operands.–There is (almos t) a one-to-one correspondence between thesemnemonics and machine instructi ons, so it is very easy toconvert assembly programs to ma chine language.•We’ll use assembly code this today to introduce the basic ideas, andswitch to machine language tomorrow.04/26/05 ISA 7Data manipulation instructions•Data manipulation instructions correspond to ALU operations.•For example, here is a possible addition instruction, and itsequivalent using our register transfer notation:•This is similar to a high-level prog ramming statement likeR0 = R1 + R2•Here, all of the operands are registers.ADD R0, R1, R2operationdestination sourcesoperandsR0  R1 + R2Register transfer instruction:04/26/05 ISA 8More data manipulation instructions•Here are some other kinds of data manipulation instructions.NOT R0, R1 R0  R1’ADD R3, R3, #1 R3  R3 + 1SUB R1, R2, #5 R1  R2 - 5•Some instructions, like the NOT, have only one operand.•In addition to register operands, constant operands like 1 and 5 arealso possible. Constants are de noted with a hash mark in f ront.04/26/05 ISA 9Relation to the datapath•These instructions reflec t the design ofour datapath from last week.•There are at most two source operandsin e ach instruction, since our ALU hasjust two inputs.•The two sources can be two registers,or one register and one constant.•More complex operations likeR0  R1 + R2 - 3must be br oken down into severallower-level instructions.•Instructions have ju st one destinationoperand, which must be a register.D dataWriteD addressA address B addressA data B dataRegister FileWRDAAA BAA BALUFZNCVFSFSS D1 D0QConstantMB04/26/05 ISA 10What about RAM?•Recall that our ALU hasdirect access only to theregister file.•RAM contents must becopied to the registersbefore they can be used asALU operands.•Similarly, ALU res ults mustgo through the registersbefore they can be s toredinto memory.•We rely on da ta movementinstructions to transfer databetween the RAM and theregister file.D dataWriteD addressA address B addressA data B dataRegister FileWRDAAA BAQ D1D0SRAMADRSDATACSWROUTMW+5VA BALUFZNCVFSFSMDS D1 D0QConstantMB04/26/05 ISA 11Loading a register from RAM•A load i nstruction copiesdata from a RAM address toone of th e registers.LD R1,(R3) R1  M[R3]•Remember in our datapath,the RAM address must comefrom one of the r egisters—in the example above, R3.•The parentheses help showwhich register operandholds the memor y address.D dataWriteD addressA address B addressA data B dataRegister FileWRDAAA BARAMADRSDATACSWROUTMW+5VA BALUFZNCVFSFSMDS D1 D0QConstantMBQ D1D0S04/26/05 ISA 12Storing a register to RAM•A store instruction copiesdata from a register to anaddress in RAM .ST (R3),R1 M[R3]  R1•One register sp ecifies theRAM address to write to—inthe example above, R3.•The other operand specifiesthe actual data to be storedinto RAM—R1 above.Q D1D0SA BALUFZNCVFSFSMDS D1 D0QConstantMBRAMADRSDATACSWROUTMW+5VD dataWriteD addressA address B addressA data B dataRegister


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U of I CS 231 - Instruction set architectures

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