1NOW Handout Page 1EECS 252 Graduate Computer ArchitectureLec 11 – Mid Term ReviewDavid CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs2522/22/2005 CS252 L11-review2Review Exercise• The 1+X “accumulator” based ISA never seems to go away because of its “minimal” processor state – witness the longevity of the 8051• You are given the task of designing a “high performance 8051”. Having learned about the separation of architected state and microarchitecture, you are ready to attack the problem. A simple analysis suggests that 8051 code has very strong sequential dependences. You will need to use serious instruction lookahead, branch prediction, and register renaming to get at the ILP.• Assume a MIPS 10K-like data path with multiple function units, lots of physical registers. You need to design the instruction issue and register mapping logic to get ILP out of this beast.• When is a physical register available for reuse?2/22/2005 CS252 L11-review3Solution Framework• ISA?• Typical sequence• Dependences• Names?• Mapping• FreePhysicalRegistersInstructionqueueROB* * *InstIssueand regmappingfwd2/22/2005 CS252 L11-review4Review of Memory Hierarchy that we skipped2/22/2005 CS252 L11-review5Recap: Who Cares About the Memory Hierarchy?µProc60%/yr.(2X/1.5yr)DRAM9%/yr.(2X/10 yrs)110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformance Gap:(grows 50% / year)PerformanceTime“Moore’s Law”Processor-DRAM Memory Gap (latency)2/22/2005 CS252 L11-review6Levels of the Memory HierarchyCPU Registers100s Bytes<10s nsCacheK Bytes10-100 ns1-0.1 cents/bitMain MemoryM Bytes200ns- 500ns$.0001-.00001 cents /bitDiskG Bytes, 10 ms (10,000,000 ns)10 - 10 cents/bit-5-6CapacityAccess TimeCostTapeinfinitesec-min10-8RegistersCacheMemoryDiskTapeInstr. OperandsBlocksPagesFilesStagingXfer Unitprog./compiler1-8 bytescache cntl8-128 bytesOS512-4K bytesuser/operatorMbytesUpper LevelLower LevelfasterLarger2NOW Handout Page 22/22/2005 CS252 L11-review7The Principle of Locality• The Principle of Locality:– Program access a relatively small portion of the address space at any instant of time.• Two Different Types of Locality:– Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon (e.g., loops, reuse)– Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon (e.g., straightline code, array access)• Last 15 years, HW relied on locality for speedIt is a property of programs which is exploited in machine design.2/22/2005 CS252 L11-review8Memory Hierarchy: Terminology• Hit: data appears in some block in the upper level (example: Block X) – Hit Rate: the fraction of memory access found in the upper level– Hit Time: Time to access the upper level which consists ofRAM access time + Time to determine hit/miss• Miss: data needs to be retrieve from a block in the lower level (Block Y)– Miss Rate = 1 - (Hit Rate)– Miss Penalty: Time to replace a block in the upper level + Time to deliver the block the processor• Hit Time << Miss Penalty (500 instructions on 21264!)Lower LevelMemoryUpper LevelMemoryTo ProcessorFrom ProcessorBlk XBlk Y2/22/2005 CS252 L11-review9Cache Measures• Hit rate: fraction found in that level– So high that usually talk about Miss rate– Miss rate fallacy: as MIPS to CPU performance, miss rate to average memory access time in memory • Average memory-access time = Hit time + Miss rate x Miss penalty (ns or clocks)• Miss penalty: time to replace a block from lower level, including time to replace in CPU– access time: time to lower level = f(latency to lower level)– transfer time: time to transfer block =f(BW between upper & lower levels)2/22/2005 CS252 L11-review10Simplest Cache: Direct MappedMemory4 Byte Direct Mapped CacheMemory Address0123456789ABCDEFCache Index0123• Location 0 can be occupied by data from:– Memory location 0, 4, 8, ... etc.– In general: any memory locationwhose 2 LSBs of the address are 0s– Address<1:0> => cache index• Which one should we place in the cache?• How can we tell which one is in the cache?2/22/2005 CS252 L11-review111 KB Direct Mapped Cache, 32B blocks• For a 2 ** N byte cache:– The uppermost (32 - N) bits are always the Cache Tag– The lowest M bits are the Byte Select (Block Size = 2 ** M)Cache Index0123:Cache DataByte 00431:Cache Tag Example: 0x50Ex: 0x010x50Stored as partof the cache “state”Valid Bit:31Byte 1Byte 31:Byte 32Byte 33Byte 63:Byte 992Byte 1023:Cache TagByte SelectEx: 0x0092/22/2005 CS252 L11-review12Two-way Set Associative Cache• N-way set associative: N entries for each Cache Index– N direct mapped caches operates in parallel (N typically 2 to 4)• Example: Two-way set associative cache– Cache Index selects a “set” from the cache– The two tags in the set are compared in parallel– Data is selected based on the tag resultCache DataCache Block 0Cache TagValid:::Cache DataCache Block 0Cache Tag Valid:::Cache IndexMux01Sel1 Sel0Cache BlockCompareAdr TagCompareORHit3NOW Handout Page 32/22/2005 CS252 L11-review13Disadvantage of Set Associative Cache• N-way Set Associative Cache v. Direct Mapped Cache:– N comparators vs. 1– Extra MUX delay for the data– Data comes AFTER Hit/Miss• In a direct mapped cache, Cache Block is available BEFORE Hit/Miss:– Possible to assume a hit and continue. Recover later if miss.Cache DataCache Block 0Cache Tag Valid:::Cache DataCache Block 0Cache TagValid:::Cache IndexMux01Sel1 Sel0Cache BlockCompareAdr TagCompareORHit2/22/2005 CS252 L11-review144 Questions for Memory Hierarchy• Q1: Where can a block be placed in the upper level? (Block placement)• Q2: How is a block found if it is in the upper level?(Block identification)• Q3: Which block should be replaced on a miss? (Block replacement)• Q4: What happens on a write? (Write strategy)2/22/2005 CS252 L11-review15Q1: Where can a block be placed in the upper level? • Block 12 placed in 8 block cache:– Fully associative, direct mapped, 2-way set associative– S.A. Mapping = Block Number Modulo Number SetsCache01234567 0123456701234567Memory111111111122222222223301234567890123456789012345678901Full MappedDirect Mapped(12 mod 8) = 42-Way Assoc(12 mod 4) =
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