EECS 252 Graduate Computer ArchitectureLec 1 - Introduction David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs2521/18/2005 CS252-s05, Lec 01-intro2Outline• What is Computer Architecture?• Computer Instruction Sets – the fundamental abstraction– review and set up• Dramatic Technology Advance• Beneath the illusion – nothing is as it appears• Computer Architecture Renaissance• How would you like your CS252?1/18/2005 CS252-s05, Lec 01-intro3What is “Computer Architecture”?ApplicationsInstruction SetArchitectureCompilerOperatingSystemFirmware• Coordination of many levels of abstraction• Under a rapidly changing set of forces• Design, Measurement, and EvaluationI/O systemInstr. Set Proc.Digital DesignCircuit DesignDatapath & Control Layout & fabSemiconductor MaterialsDie photoApp photo1/18/2005 CS252-s05, Lec 01-intro4Forces on Computer ArchitectureComputerArchitectureTechnologyProgrammingLanguagesOperatingSystemsHistoryApplications(A = F / M)1/18/2005 CS252-s05, Lec 01-intro5The Instruction Set: a Critical Interfaceinstruction setsoftwarehardware• Properties of a good abstraction– Lasts through many generations (portability)– Used in many different ways (generality)– Provides convenient functionality to higher levels– Permits an efficient implementation at lower levels1/18/2005 CS252-s05, Lec 01-intro6Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. – Amdahl, Blaaw, and Brooks, 1964SOFTWARESOFTWARE-- Organization of Programmable Storage-- Data Types & Data Structures:Encodings & Representations-- Instruction Formats-- Instruction (or Operation Code) Set-- Modes of Addressing and Accessing Data Items and Instructions-- Exceptional Conditions1/18/2005 CS252-s05, Lec 01-intro7Computer OrganizationLogic Designer's ViewISA LevelFUs & Interconnect• Capabilities & Performance Characteristics of Principal Functional Units– (e.g., Registers, ALU, Shifters, Logic Units, ...)• Ways in which these components are interconnected• Information flows between components• Logic and means by which such information flow is controlled.• Choreography of FUs to realize the ISA• Register Transfer Level (RTL) Description1/18/2005 CS252-s05, Lec 01-intro8Fundamental Execution CycleInstructionFetchInstructionDecodeOperandFetchExecuteResultStoreNextInstructionObtain instruction from program storageDetermine required actions and instruction sizeLocate and obtain operand dataCompute result value or statusDeposit results in storage for later useDetermine successor instructionProcessorregsF.U.sMemoryprogramDatavon Neumanbottleneck1/18/2005 CS252-s05, Lec 01-intro9Elements of an ISA• Set of machine-recognized data types– bytes, words, integers, floating point, strings, . . .• Operations performed on those data types– Add, sub, mul, div, xor, move, ….• Programmable storage– regs, PC, memory• Methods of identifying and obtaining data referenced by instructions (addressing modes)– Literal, reg., absolute, relative, reg + offset, …• Format (encoding) of the instructions– Op code, operand fields, …Current Logical Stateof the MachineNext Logical Stateof the Machine1/18/2005 CS252-s05, Lec 01-intro10Example: MIPS R30000r0r1°°°r31PClohiProgrammable storage2^32 x bytes31 x 32-bit GPRs (R0=0)32 x 32-bit FP regs (paired DP)HI, LO, PCData types ?Format ?Addressing Modes?Arithmetic logical Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUISLL, SRL, SRA, SLLV, SRLV, SRAVMemory AccessLB, LBU, LH, LHU, LW, LWL,LWRSB, SH, SW, SWL, SWRControlJ, JAL, JR, JALRBEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL32-bit instructions on word boundary1/18/2005 CS252-s05, Lec 01-intro11Evolution of Instruction SetsSingle Accumulator (EDSAC 1950)Accumulator + Index Registers(Manchester Mark I, IBM 700 series 1953)Separation of Programming Modelfrom ImplementationHigh-level Language Based (Stack) Concept of a Family(B5000 1963) (IBM 360 1964)General Purpose Register MachinesComplex Instruction Sets Load/Store ArchitectureRISC(Vax, Intel 432 1977-80)(CDC 6600, Cray 1 1963-76)(MIPS,Sparc,HP-PA,IBM RS6000, 1987)iX86?1/18/2005 CS252-s05, Lec 01-intro12Dramatic Technology Advance• Prehistory: Generations– 1stTubes– 2ndTransistors– 3rdIntegrated Circuits– 4thVLSI….• Discrete advances in each generation– Faster, smaller, more reliable, easier to utilize• Modern computing: Moore’s Law– Continuous advance, fairly homogeneous technology1/18/2005 CS252-s05, Lec 01-intro13Moore’s Law• “Cramming More Components onto Integrated Circuits”– Gordon Moore, Electronics, 1965• # on transistors on cost-effective integrated circuit double every 18 months1/18/2005 CS252-s05, Lec 01-intro14Year1000100001000001000000100000001000000001970 1975 1980 1985 1990 1995 2000i80386i4004i8080Pentiumi80486i80286i8086Technology Trends: Microprocessor CapacityCMOS improvements:• Die size: 2X every 3 yrs• Line width: halve / 7 yrsItanium II: 241 millionPentium 4: 55 millionAlpha 21264: 15 millionPentium Pro: 5.5 millionPowerPC 620: 6.9 millionAlpha 21164: 9.3 millionSparc Ultra: 5.2 millionMoore’s Law1/18/2005 CS252-s05, Lec 01-intro15sizeYear10001000010000010000001000000010000000010000000001970 1975 1980 1985 1990 1995 2000Memory Capacity (Single Chip DRAM)year size(Mb) cyc time1980 0.0625 250 ns1983 0.25 220 ns1986 1 190 ns1989 4 165 ns1992 16 145 ns1996 64 120 ns2000 256 100 ns2003 1024 60 ns1/18/2005 CS252-s05, Lec 01-intro16Technology Trends • Clock Rate: ~30% per year• Transistor Density: ~35%• Chip Area: ~15%• Transistors per chip: ~55%• Total Performance Capability: ~100%• by the time you graduate...– 3x clock rate (~10 GHz)– 10x transistor count (10 Billion transistors)– 30x raw capability• plus 16x dram density, • 32x disk density (60% per year)• Network bandwidth, …1/18/2005 CS252-s05, Lec 01-intro17Performance0.11101001965 1970 1975 1980 1985 1990 1995SupercomputersMinicomputersMainframesMicroprocessorsPerformance Trends1/18/2005 CS252-s05, Lec 01-intro1802004006008001000120087 88 89 90 91 92 93 94 95 96 97DEC Alpha 21164/600DEC Alpha
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