Smart Dust Mote Core ArchitectureSmart Dust OverviewSystem DiagramDesign GoalsDesired OperationsOne Approach: ‘Golden Processor’Golden Processor: FeaturesNew Approach: Top-Level DiagramTimers and Setup MemoryReconfigurable Datapath ComponentsExample Configuration: Sensor LoggingComparison of Three ArchitecturesConclusionsSmart Dust Mote Core ArchitectureSmart Dust Mote Core ArchitectureBrett Warneke, Sunil BhaveCS252Spring 2000Smart Dust Mote Core ArchitectureSmart Dust Overview•Autonomous sensing and communications in 1 mm3 •Multiple sensors: temperature, light, vibration, etc.•Batteries: 1 J/mm3 •Downlink:broadcast only•Uplink: CCR draws 6.4pJ/bit1 - 2 m mT h i c k - F i l m B a t t e r yS o l a r C e l lP o w e r C a p a c i t o rA n a l o g I / O , D S P , C o n t r o lP a s s i v e T r a n s m i t t e r w i t hC o r n e r - C u b e R e t r o r e f l e c t o rS e n s o r sR e c e i v e r w i t h P h o t o d e t e c t o rSmart Dust Mote Core ArchitectureSystem Diagram Core•Transceiver back end•Sensor Signal Processing•Computation•MemorySensorsPower SupplyReceiver Front EndADCReal Time ClockCCR DriverSmart Dust Mote Core ArchitectureDesign Goals•Minimize energy through architecture–Minimum energy ASIC implementation•Dynamic reconfigurability–How much is necessary tradeoff with ASIC mapping–Energy driven operation modes•Military base monitoring–Typical application scenario to guide design–Detect heat and vibration of vehicles–Real time sensor readings–Logged sensor readingsASIC MicroprocessorSmart Dust Mote Core ArchitectureDesired Operations•Immediate–Transmit ID Mote health report–Transmit current readings from one/all sensors–Send logged data for sensor X–Calibrate real-time clock• Reconfiguration– Start logging data from sensor X sampled every T seconds– Set logging threshold and filter coefficients– Set ‘ScatterCast’ interval to T seconds– Set your wakeup interval to T secondsSmart Dust Mote Core ArchitectureOne Approach: ‘Golden Processor’Smart Dust Mote Core ArchitectureGolden Processor: Features•Laser Reprogrammable•Gated clocks everywhere•Processor stall mode•Eight execution phases–1 cpi including fetch–No pipelining to reduce overhead–Forced sequencing•Minimize glitching•Prevent bus conflicts and thus short circuit current–Robust to delay variations from process spreads, voltage swings (will test from 0.3V to 1.4V), and temperatureSmart Dust Mote Core ArchitectureNew Approach: Top-Level DiagramSensorsPower SupplyReceiver Front EndADCReal Time ClockCCR DriverTimer BankSetup MemroyReconfigurable Datapath ComponentsSRAMSmart Dust Mote Core Architecture•All activity initiated by timers–When timer expires, Setup Memory 1 configures the datapath–Additional setup memories can be invoked to perform more steps•Two rates available for each timer–Two sensor sampling rates for normal polling and interesting events–Delay receiver for a long period before returning to normal rate•Multiple setup memory banks for energy-driven operationmodesTimers and Setup MemoryTimer value 1Timer value 2TimerSetup Mem 1Setup Mem 2Smart Dust Mote Core ArchitectureReconfigurable Datapath ComponentsAdderTiming RecoveryMote ID MemData Addr RegSensor Reg nComparator Threshold Mem nPacket Decoder Config MemFFT Config MemFIR FilterData RecoveryPacket EncoderCRCFIFOImmediate Mode Setup Reg•Immediate mode packets load Immediate Mode Setup Register to configure the datapath•Data-driven components•Wiring options–many point-to-point control and data wires–wire mesh with switches for routingGlobal Setup RegSmart Dust Mote Core ArchitectureExample Configuration: Sensor LoggingTimer value 1Timer value 2TimerSetup Mem 1Setup Mem 2AdderData Addr RegSensor RegComparator Threshold MemSensorADCSRAMPWR PWRPWRPWRPWRDoneDataDoneDataPWRPWRAddrDataZeroWETrueFalseDoneOpen control signals are driven by the setup memory543210 ZeroSetup Mem 1Open control signals are driven by the setup memorySensor RegSensorADCPWR PWRPWRPWRPWRDoneDataPWRPWRDoneDataAdder Threshold MemDoneDataPWRDoneDataPWRComparatorFalseTrueTrueData Addr RegSRAMPWRAddrDataWEDoneSetup Mem 1Setup Mem 2AdderData Addr RegSensor RegComparator Threshold MemSensorADCSRAMPWR PWRPWRPWRPWRDoneDataDoneDataPWRPWRAddrDataWETrueFalseDoneOpen control signals are driven by the setup memorySetup Mem 2Open control signals are driven by the setup memorySmart Dust Mote Core ArchitectureComparison of Three Architectures•ARM8 estimations from Peggy Laramie, M.S. thesis 1998–energy is for a set of instructions equivalent to the configuration on the previous slide–Vdd=1V (scaled from the reported numbers)•Energy estimations for other approaches were to be from PowermillARM8 GoldenProcessorNewArchitectureDatalogging w/threshold1.44nJSmart Dust Mote Core ArchitectureConclusions•Smart Dust needs minimum energy controller•New non-microprocessor architecture designed–Timer controlled–Reconfigurable datapath–Should be much lower energy than a microprocessor architecture, but
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