CS252 Graduate Computer Architecture Lecture 7 Cache Design (continued)How to Improve Cache Performance?Where to misses come from?3Cs Absolute Miss Rate (SPEC92)Reducing Misses by Hardware Prefetching of Instructions & DataReducing Misses by Software Prefetching DataReducing Misses by Compiler OptimizationsMerging Arrays ExampleLoop Interchange ExampleLoop Fusion ExampleBlocking ExampleSlide 12Reducing Conflict Misses by BlockingSummary of Compiler Optimizations to Reduce Cache Misses (by hand)Summary: Miss Rate ReductionReview: Improving Cache PerformanceWrite Policy: Write-Through vs Write-BackWrite Policy 2: Write Allocate vs Non-Allocate (What happens on write-miss)1. Reducing Miss Penalty: Read Priority over Write on MissSlide 202. Reduce Miss Penalty: Early Restart and Critical Word First3. Reduce Miss Penalty: Non-blocking Caches to reduce stalls on missesValue of Hit Under Miss for SPEC4: Add a second-level cachePartner DiscussionComparing Local and Global Miss RatesReducing Misses: Which apply to L2 Cache?L2 cache block size & A.M.A.T.Reducing Miss Penalty SummaryWhat is the Impact of What You’ve Learned About Caches?1. Fast Hit times via Small and Simple CachesAddress TranslationTLBsTranslation Look-Aside Buffers2. Fast hits by Avoiding Address Translation2. Fast Cache Hits by Avoiding Translation: Index with Physical Portion of Address2. Fast hits by Avoiding Address Translation3: Fast Hits by pipelining Cache Case Study: MIPS R4000Case Study: MIPS R4000R4000 PerformanceSlide 41Alpha 21064Alpha Memory Performance: Miss Rates of SPEC92Alpha CPI ComponentsPitfall: Predicting Cache Performance from Different Prog. (ISA, compiler, ...)Cache Optimization SummaryCS252/CullerLec 4.11/31/02CS252Graduate Computer ArchitectureLecture 7Cache Design (continued)Feb 12, 2002Prof. David CullerCS252/CullerLec 4.21/31/02How to Improve Cache Performance?1. Reduce the miss rate, 2. Reduce the miss penalty, or3. Reduce the time to hit in the cache. yMissPenaltMissRateHitTimeA MAT CS252/CullerLec 4.31/31/02Where to misses come from?•Classifying Misses: 3 Cs–Compulsory—The first access to a block is not in the cache, so the block must be brought into the cache. Also called cold start misses or first reference misses.(Misses in even an Infinite Cache)–Capacity—If the cache cannot contain all the blocks needed during execution of a program, capacity misses will occur due to blocks being discarded and later retrieved.(Misses in Fully Associative Size X Cache)–Conflict—If block-placement strategy is set associative or direct mapped, conflict misses (in addition to compulsory & capacity misses) will occur because a block can be discarded and later retrieved if too many blocks map to its set. Also called collision misses or interference misses.(Misses in N-way Associative, Size X Cache)•4th “C”:–Coherence - Misses caused by cache coherence.CS252/CullerLec 4.41/31/02Cache Size (KB) Miss Rate per Type00.020.040.060.080.10.120.1412481632641281-way2-way4-way8-wayCapacity Compulsory 3Cs Absolute Miss Rate (SPEC92)ConflictCS252/CullerLec 4.51/31/02Reducing Misses by Hardware Prefetching of Instructions & Data •E.g., Instruction Prefetching–Alpha 21064 fetches 2 blocks on a miss–Extra block placed in “stream buffer”–On miss check stream buffer•Works with data blocks too:–Jouppi [1990] 1 data stream buffer got 25% misses from 4KB cache; 4 streams got 43%–Palacharla & Kessler [1994] for scientific programs for 8 streams got 50% to 70% of misses from 2 64KB, 4-way set associative caches•Prefetching relies on having extra memory bandwidth that can be used without penaltyCS252/CullerLec 4.61/31/02Reducing Misses by Software Prefetching Data•Data Prefetch–Load data into register (HP PA-RISC loads)–Cache Prefetch: load into cache (MIPS IV, PowerPC, SPARC v. 9)–Special prefetching instructions cannot cause faults; a form of speculative execution•Prefetching comes in two flavors:–Binding prefetch: Requests load directly into register.»Must be correct address and register!–Non-Binding prefetch: Load into cache. »Can be incorrect. Faults?•Issuing Prefetch Instructions takes time–Is cost of prefetch issues < savings in reduced misses?–Higher superscalar reduces difficulty of issue bandwidthCS252/CullerLec 4.71/31/02Reducing Misses by Compiler Optimizations•McFarling [1989] reduced caches misses by 75% on 8KB direct mapped cache, 4 byte blocks in software•Instructions–Reorder procedures in memory so as to reduce conflict misses–Profiling to look at conflicts(using tools they developed)•Data–Merging Arrays: improve spatial locality by single array of compound elements vs. 2 arrays–Loop Interchange: change nesting of loops to access data in order stored in memory–Loop Fusion: Combine 2 independent loops that have same looping and some variables overlap–Blocking: Improve temporal locality by accessing “blocks” of data repeatedly vs. going down whole columns or rowsCS252/CullerLec 4.81/31/02Merging Arrays Example/* Before: 2 sequential arrays */int val[SIZE];int key[SIZE];/* After: 1 array of stuctures */struct merge {int val;int key;};struct merge merged_array[SIZE];Reducing conflicts between val & key; improve spatial localityCS252/CullerLec 4.91/31/02Loop Interchange Example/* Before */for (k = 0; k < 100; k = k+1)for (j = 0; j < 100; j = j+1)for (i = 0; i < 5000; i = i+1)x[i][j] = 2 * x[i][j];/* After */for (k = 0; k < 100; k = k+1)for (i = 0; i < 5000; i = i+1)for (j = 0; j < 100; j = j+1)x[i][j] = 2 * x[i][j];Sequential accesses instead of striding through memory every 100 words; improved spatial localityCS252/CullerLec 4.101/31/02Loop Fusion Example/* Before */for (i = 0; i < N; i = i+1)for (j = 0; j < N; j = j+1)a[i][j] = 1/b[i][j] * c[i][j];for (i = 0; i < N; i = i+1)for (j = 0; j < N; j = j+1)d[i][j] = a[i][j] + c[i][j];/* After */for (i = 0; i < N; i = i+1)for (j = 0; j < N; j = j+1){ a[i][j] = 1/b[i][j] * c[i][j];d[i][j] = a[i][j] + c[i][j];}2 misses per access to a & c vs. one miss per access; improve spatial localityCS252/CullerLec 4.111/31/02Blocking Example/* Before */for (i = 0; i < N; i = i+1)for (j = 0; j < N; j = j+1){r = 0; for (k = 0; k < N; k = k+1){r = r + y[i][k]*z[k][j];}; x[i][j] = r;};•Two Inner Loops:–Read all NxN elements of z[]–Read N elements of 1 row of y[] repeatedly–Write N elements of 1 row of x[]•Capacity Misses a function of N & Cache Size:–2N3 + N2 => (assuming no
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