0.000.100.200.300.400.500.600.700.800.901.002.00 4.001 : No overhead2 : Simple parallel-pipeline datapath3 : Simple parallel datapath4 : 7th order IIR filter5 : Overhead ∝ N26 : Overhead ∝ N31234561.005.003.00Figure 10: Optimum voltage of operation.Vdd(volts)NORMALIZED POWERVoltageIIRParallel-1.51.411 / 0.136 / 0.1915 / 0.147 / 0.123.7 / 0.27 / 0.142.6 / 0.23Recursivebottleneck10 / 0.11ParallelTable 3: Normalized Area/Power for various supply voltages for Plots 2,3,4 in Figure 10.2Pipelinereachedarea/powerarea/powerarea/power1 / 1 1 / 1 1 / 151T1TAB1TCCOMPARATORA> B1T1TFigure 9: Pipelined implementation of the simple datapath.LATCH AADDERLATCH BLATCH PCOMPARATORLATCH C2LATCH C1Area = 640 x 1081 µ2Architecture typePowerAreaSimple datapath(no pipelining orparallelism)11Pipelined datapathParallel datapath1.33.40.360.39Pipeline-Parallel 3.70.2Voltage5V2.9V2.9V2.0VTable 2: Architecture summary.1T1TAB1TCCOMPARATORA>BFigure 7: A simple datapath with corresponding layout.LATCH ALATCH BLATCH CCOMPARATORADDERArea = 636 x 833 µ212TABCCOMPARATORA>B12T12T12TCCOMPARATORA>B12T12T1 TLATCH ALATCH BLATCH CCOMPARATORADDERLATCH ALATCH BLATCH CCOMPARATORADDERMUXFigure 8: Parallel implementation of the simple datapath.Area = 1476 x 1219 µ2α = 0 adder0.50.71.01.523457101 3 10α = 0.5α = 1α = 1.5α = 2N, W/L SIZING FACTORNORMALIZED ENERGYFigure 6: Plot of energy vs. transistor sizing factor for various parasitic contributions. Cp = Cwiring + Cjunction Cg= NCref I ∝ N CrefFigure 5: Circuit model for analyzing the effect of transistor sizing.Figure 4: Data showing improvement in power-delay product at the cost of speed forvarious circuit approaches.35710152030507010015020010 30 1003254618-bit adders in 2.0µmPOWER-DELAY PRODUCT (pJ)DELAY (ns)DecreasingVdd1 : Pass-transistor Logic (CPL) - SPICE [8]2 : Optimized Static (with Propagate/Generate logic)[10]3 : Conventional Static[10]4 : Standard Cell [22]5 : Carry Select [10]6 : Differential-Cascode Voltage SwitchLogic (dynamic) - SPICE [13]1.001.502.002.503.003.504.004.505.005.506.006.507.007.502.00 4.00 6.00Vdd (volts)NORMALIZED DELAYComponentCommentsAreaMultiplierClock GeneratorAdder# of20432448025625612.2mm294mm2Microcoded DSP Chip24x24 bits20-bit datapathcross-coupled0.04mm2conventionalstaticRing Oscillator102 51-stages0.055mm20.083mm2 transistors(all in 2µm) NORTable 1: Details of components used for the study in Figure 3.[21]Figure 3: Data demonstrating delay characteristics follow simple first order theory.adder (SPICE)microcoded DSP chipmultiplieradderring oscillatorclock generator2.0µm technology0.030.050.070.10.150.200.300.500.701.001.51 2 5211: 51 stage ring oscillator2: 8-bit ripple-carry adderFigure 2: Power-delay product exhibiting square law dependence for two different circuits.Vdd (volts)quadratic dependenceNORMALIZED POWER-DELAY PRODUCTAABBC CGNDVDDAABBABABABABSumBCABAVDDABABVDDCoutAABBCCAAB BCCSum SumACCBCoutCoutBAAA AFigure 1: Comparison of a Conventional CMOS and CPL adders [8].Transistor count (conventional CMOS) : 40Transistor count (CPL) : 28Conclusions18 of 18[6] G. Geschwind and R.M. Clary, ‘‘Multichip Modules- An Overview’’, Expo SMT/HiDEP 1990 Technical Proceedings,San Jose, CA, 1990.[7] D.A. Patterson and C.H. Sequin, “Design Considerations for Single-Chip Computers of the Future”, Joint SpecialIssue, IEEE Journal of Solid-State Circuits SC-15, No.1 and IEEE Transactions on Computers C-29, No.2, pp. 108-116, Feb. 1980.[8] K. Yano, et al., ‘‘A 3.8ns CMOS 16x16 Multiplier Using Complementary Pass Transistor Logic’’, IEEE Journal ofSolid-State Circuits, pp. 388-395, April 1990.[9] H.J.M. Veendrick, ‘‘Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Cir-cuts’’, IEEE Journal of Solid-State Circuits, Vol. SC-19, pp. 468-473, August 1984.[10] N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, Addison-Wesley, MA, 1988.[11]R.K. Watts (ed.), Submicron Integrated Circuits, John Wiley & Sons, NY, 1989.[12]D. Green, Modern Logic Design , Addison-Wesley, pp. 15-17, 1986.[13] G.Jacobs and R.W. Brodersen, “A Fully Asynchronous Digital Signal Processor Using Self-Timed Circuits”, IEEEJournal of Solid-State Circuits, pp. 1526-1537, December 1990.[14]D. Hodges and H. Jackson, Analysis and Design of Digital Integrated Circuits, McGraw-Hill, Inc., 1988.[15] M. Shoji, CMOS Digital Circuit Technology, Prentice-Hall,1988.[16]S. Sze, Physics of Semiconductor Devices, John Wiley & Sons, 1981.[17]M. Aoki et al., “0.1µm CMOS Devices Using Low-Impurity-Channel Transistors (LICT)”, IEDM, pp. 939-941, 1990.[18]M. Nagata, “Limitations, Innovations, and Challenges of Circuits & Devices into Half-Micron and Beyond”, Sympo-sium on VLSI circuits, pp. 39-42, 1991.[19]S.C. Ellis, “Power Management in Notebook PC’s”, Silicon Valley Personal Computer Conference, pp. 749-754,1991.[20]K. Chu and D. Pulfrey, “A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Ver-sus Conventional Logic”, IEEE Journal of Solid-State Circuits, pp. 528-532, August 1987.[21]R.W. Brodersen, Lager: A Silicon Compiler, to be published, Kluwer.[22]R.W. Brodersen et. al., LagerIV Cell Library Documentation, Electronics Research Laboratory, University of Califor-nia, Berkeley, June 23, 1988.[23]B. Davari et al., “A High Performance 0.25µm CMOS Technology”, IEDM, pp. 56-59, 1988.[24] M. Kakumu and M Kinugawa, “Power-Supply Voltage Impact on Circuit Performance for Half and Lower Submi-crometer CMOS LSI”, IEEE Transactions on Electron Devices, Vol 37, No. 8, pp. 1902-1908, August 1990.[25]D. Dahle, “Designing High Performance Systems to Run from 3.3V or Lower Sources”, Silicon Valley Personal Com-puter Conference, pp. 685-691, 1991.[26]R. Swansan and J. Meindl, “Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits”, IEEE Journalof Solid-State Circuits, pp. 146-153, April 1972.[27]D. Messerschmitt: “Breaking the Recursive Bottleneck”, Skwirzynski (editor), Performance Limits in Communica-tion Theory and Practice, pp. 3-19, 1988.[28]M. Potkonjak and J. Rabaey, “Optimizing Resource Utilization using Transformations”, ICCAD, pp. 88-91, Novem-ber 1991.Conclusions17 of 18With the continuing trend of denser technology through scaling and the development of advanced packagingtechniques, a new degree of freedom in architectural design has been made possible in which silicon area canbe traded off
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