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Berkeley COMPSCI 252 - Lecture 21

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Lecture 21: Goodbye to Computer Arhcitecture and How to Have a Bad Career in Research/AcademiaReview of CourseChapter 5: Memory HierarchyCache Optimization SummaryGoodbye to Memory HierarchyChapter 6: Storage I/OGoodbye to Storage I/OSlide 8Chapter 7: NetworksSlide 10Goodbye to NetworkingChapter 8: MultiprocessorsGoodbye to MultiprocessorsChapter 2: Instruction Set ArchitectureGoodbye to Instruction Set ArchitectureGoodbye to Dynamic Execution (Chapter 3)Goodbye to Static, EmbeddedGoodbye to Computer ArchitectureAdministratriviaOutlinePart I: How to Have a Bad Graduate CareerSlide 22Part II: Alternatives to a Bad Graduate CareerSlide 24Slide 25Part II: How to be a Success in Graduate SchoolSlide 27Bad Career Move #1: Be THE leading expertAnnouncing a New Operating System Field: “Disability Based Systems”Announcing yet another New O.S. Field: “Omni-Femtokernels”Bad Career Move #2: Let Complexity Be Your Guide (Confuse Thine Enemies)Bad Career Move #3: Never be Proven WrongBad Career Move #4: Use the Computer Scientific MethodBad Career Move #5: Don’t be Distracted by Others (Avoid Feedback)Bad Career Move #6: Publishing Journal Papers IS Technology TransferBad Career Move #7: Writing Tactics for a Bad Career5 Writing Commandments for a Bad Career7 Talk Commandments for a Bad CareerFollowing all the commandmentsSlide 40One Alternative Strategy to a Bad Career1) Selecting a ProblemMy first project (“Xtree”)2) Picking a solution(And Pick A Good Name!)3) Running a project4) Finishing a project5) Evaluating Quantitatively6) Transferring6) Transferring TechnologySummary: Leader’s Role Changes during ProjectAcknowledgmentsConclusion: Alternatives to a Bad CareerSlide 54Applying the Computer Scientific Method to OSDAP Spr.‘01 ©UCB 1Lecture 21: Goodbye to Computer Arhcitecture Goodbye to Computer Arhcitecture and How to Have a Bad Career and How to Have a Bad Career in Research/Academia in Research/Academia Professor David A. PattersonComputer Science 252Spring 2001DAP Spr.‘01 ©UCB 2Review of Course•Review and Goodbye to Computer Architecture, topic by topic + follow-on courses•How to have a bad career•HKN teaching evaluation last 15 minutesDAP Spr.‘01 ©UCB 3Chapter 5: Memory Hierarchy•Processor-DRAM Performance gap•1/3 to 2/3 die area for caches, TLB•Alpha 21264: 108 clock to memory 648 instruction issues during miss•3 Cs: Compulsory, Capacity, Conflict•4 Questions: where, who, which, write•Applied recursively to create multilevel caches•Performance = f(hit time, miss rate, miss penalty)–danger of concentrating on just one when evaluating performanceMPU60%/yr.DRAM7%/yr.DAP Spr.‘01 ©UCB 4Cache Optimization SummaryTechnique MR MP HT ComplexityLarger Block Size + – 0Higher Associativity + – 1Victim Caches + 2Pseudo-Associative Caches + 2HW Prefetching of Instr/Data + 2Compiler Controlled Prefetching + 3Compiler Reduce Misses + 0Priority to Read Misses + 1Subblock Placement + + 1Early Restart & Critical Word 1st + 2Non-Blocking Caches + 3Second Level Caches + 2Small & Simple Caches – + 0Avoiding Address Translation + 2Pipelining Writes + 1miss ratehit timemisspenaltyCPUtime IC  CPIExecutionMemory accessesInstructionMiss rate Miss penaltyClock cycle timememory hierarchy art: taste in selecting between alternatives to find combination that fits well togetherDAP Spr.‘01 ©UCB 5Goodbye to Memory Hierarchy•Will L2 cache keep growing? (e.g, 64 MB L2 cache?)•Will multilevel hierarchy get deeper? (L4 cache?)•Will DRAM capacity/chip keep going at 4X / 4 years? (e.g., 16 Gbit chip?)•Will processor and DRAM/Disk be unified? For which apps?•Out-of-order CPU hides L1 data cache miss (3–5 clocks), but hide L2 miss? (>100 clocks)•Memory hierarchy likely overriding issue in algorithm performance: do algorithms and data structures of 1960s work with machines of 2000s?DAP Spr.‘01 ©UCB 6Chapter 6: Storage I/O•Disk BW 40%/yr, areal density 60%/ yr, $/MB faster?•Little’s Law: Lengthsystem = rate x Timesystem (Mean number customers = arrival rate x mean service time)–Througput vs. response time–Value of faster response time on productivity•Benchmarks: scaling, cost, auditing,response time limits•RAID: performance and reliability•Queueing theory? IEOR 161, 267, 268•CS262-A: Advanced Topics in Computer SystemsProc IOC DeviceQueueserverSystem135DAP Spr.‘01 ©UCB 7Goodbye to Storage I/O•Disks attached directly to networks, avoiding the file server? (“Network Attached Storage Devices”)•Disks:–Extraodinary advance in capacity/drive, $/GB–Currently 17 Gbit/sq. in. ; can continue past 100 Gbit/sq. in.?–Bandwidth, seek time not keeping up: 3.5 inch form factor makes sense? 2.5 inch form factor in near future? 1.0 inch form factor in long term?–Heading towards a personal terabyte: hierarchical file systems vs. database to organize personal storage?–What going to do when can have video record of entire life on line?–Will Patterson continue get email messages to reduce file storage for the rest of his career?•Tapes–No investment, must be backwards compatible–Are they already dead?–What is a tapeless backup system?DAP Spr.‘01 ©UCB 8Goodbye to Storage I/O•I/O Benchmarks: Must scale to track technological change•TPC: price performance as normalizing configuration feature–Auditing to ensure no foul play–Throughput with restricted response time is normal measure•Terminology of Fault/Error/Failure•Is Availability the killer metric for Service oriented world?•Can we construct systems that will actually achieve 99.999% availability, including software and people?•Benchmarks to measure Availability, Maintainability thereby creating a competitive environment?•Interested in learning more on HW/SW Availability/Maintability? CS 294-4 “High Confidence Computing” Fall 01 (Patterson, Armando Fox, Stanford): 10 students from Berkeley, 10 from Stanford; at Berkeley Thursdays 3-6DAP Spr.‘01 ©UCB 9Chapter 7: NetworksSenderReceiverSenderOverheadTransmission time(size ÷ bandwidth)Transmission time(size ÷ bandwidth)Time ofFlightReceiverOverheadTransport LatencyTotal Latency = Sender Overhead + Time of Flight + Message Size ÷ BW + Receiver OverheadTotal Latency(processorbusy)(processorbusy)High BW networks + high overheads violate of Amdahl’s LawDAP Spr.‘01 ©UCB 10Chapter 7: Networks•Similarities of SANs, LANs,


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Berkeley COMPSCI 252 - Lecture 21

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