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Berkeley COMPSCI 252 - Quiz

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Last Name _______________________ First Name _____________________NameMean RAIDQuestion #1: Mean RAID Question (Disk Availability) (12 points) [30 minutes]CS252 QUIZ #1: 3/7/01 D. A. PattersonLast Name _______________________ First Name _____________________Question Name Time (minutes) Max Points Your Points1 Mean RAID 30 122 Flat wallet 30 123 A 2D Neighborhood 45 16TOTAL 105 40CS252-Quiz #1, Spring 2001 Your last name: ______________________Question #1: Mean RAID Question (Disk Availability) (12 points) [30 minutes]Let’s compare two RAID disk arrays, both with 1 terabyte of user data storage capacity. (Assume 1 Gbyte = 1000 Mbytes, and 1 terabyte = 1000 Gbytes.)System I: Consists of 100 GB capacity IDE disks, each rated at 500,000 hours MTTF (Mean Time To Fail). Assume these rotate at 7200 RPM, and that the average data transfer rate for user information is 25 Mbytes per second. It is organized as a RAID 1 array with no standby spares.System S: Consists of 100 GB capacity SCSI disks, each rated at 1,000,000 hours MTTF. Assume these rotate at 10000 RPM, and that the average data transfer rate for user information is33.33 Mbytes per second. It is organized as a RAID 5 array as a single parity group plus one hot standby spare disk. (When a disk fails and is replaced, it becomes the new hot spare.)a) (2 points) First, what is the number of disks (N) in each system?System I System SNI = NS =Assume that a system administrator checks these systems once an hour to see if a disk needs to be replaced. If a disk needs to be replaced, it takes one-half hour total to find a replacement disk from the basement, to remove the bad disk, and to insert the good one. Assume that the software on both systems detects the failure immediately, and that the software on System S can begin immediately recreating the lost data onto the hot standby spare. Assume both systems have sufficient interconnection bandwidth and RAID controller hardware that they can operate at full bandwidth in all circumstances.b) (2 points) What is the formula for Mean Time To Repair lost data in System I? List any extra assumptions you need to make.MTTRI = Now calculate Mean Time To Repair lost data in System I given the parameters above. Give the answer in hours. MTTRI =c) (2 points) What is the formula for Mean Time To Repair lost data in System S? List any extra assumptions you need to make.MTTRS = Now calculate Mean Time To Repair lost data in System S given the parameters above.Give the answer in hours. MTTRS =2CS252-Quiz #1, Spring 2001 Your last name: ______________________Question #1 continued:d) (1 point) Which has better MTTR? _________ In one sentence say why.e) (2 points) What is the formula for Mean Time To Data Loss in System I? List any extra assumptions you need to make.MTTDLI =Now calculate Mean Time To Data Loss I given the parameters above.Give the answer in million hours (Mh).MTTDLI =f) (2 points) What is the formula for Mean Time To Data Loss in System S? List any extra assumptions you need to make.MTTDLS =Now calculate Mean Time To Data Loss S given the parameters aboveGive the answer in million hours (Mh).MTTDLS =g) (1 point) Which has better MTTDL? _________Explain in one sentence, listing the reasons inapproximate order of importance.3CS252-Quiz #1, Spring 2001 Your last name: ______________________Question #2: Flat wallet question (Compressed ICache) (12 points) [30 minutes] A system with a 1 GHz clock uses a separate data and instruction caches, and a unified second-level cache. The first-level instruction cache is a direct-mapped cache with 4 K bytes of data totaland 16 byte blocks. The first-level data cache is a direct-mapped, write-through, write-allocatecache with 16 K bytes of data total and 16 byte blocks, and has a perfect write buffer (nevercauses any stalls). The second-level cache is a 2-way set associative, write-back, write-allocatecache with 2M bytes of data total and 32 byte blocks. These parameters are summarized below.Cache Size Block size Associativity Write PolicyL1 Instruction 4 KB 16 B Direct mapped --L1 Data 16 KB 16 B Direct mapped Write ThroughL2 Unified 2 MB 32 B 2-way Write BackAll first-level cache hits cause no stalls. The second-level hit time is 10 clock cycles.This means the L1 miss penalty, assuming a hit in the second-level cache, is 10 clock cycles.Assume all first-level caches have hit rate as according to Table 1. Assume second-level cachehas perfect hit rate (100%). Assume 40% of all instructions are data memory accesses. Assumewith perfect first-level caches, the system has a base CPI of 1. Table 1: Miss rate for direct-mapped cachesCache sizeBlock size (byte) 4 KB 16 KB16 8.57% 3.94%32 7.79% 3.29%64 7.00% 2.64%a) (2 points) What is the CPI of the system with the above configuration? Write out the CPI formula in the box below.CPI Formula =Show the calculation:CPI=__________4CS252-Quiz #1, Spring 2001 Your last name: ______________________Question #2 continued:There are many ways to improve the cache performance. Besides the ones described in the class,one can use instruction cache compression. Because the cache is compressed, the resulting cache will appear larger by containing more content. This will give a better hit rate and thereforebetter cache performance. To do this the original program is compressed. Since the compressionwill shift the instruction addresses, a translation is needed between the compressed address and the original uncompressed address that the program understands. This is similar to the virtual memory, where translation between the virtual address and physical address is required. A table is attached to the compressed program to provide information for translation between the compressed address and the original address. For instruction access during execution, the uncompressed memory address for the instruction need to be first translated to the compressed address. The memory content at the compressed address is then fetched. The fetched content is then decompressed before execution. The following figure describes the flow during execution.Since only decompression is carried out during program execution, asymmetric compressions areusually used to minimize decompression time. Consequently, the compression and table calculation usually take a considerable time. But because these are done at compile time, it is relatively unimportant.b) (4 points) Now let's evaluate a compress instruction cache. Assume the compression


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Berkeley COMPSCI 252 - Quiz

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