EECS 252 Graduate Computer ArchitectureLec 1 - Introduction David PattersonElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~pattrsnhttp://www-inst.eecs.berkeley.edu/~cs2521/21/2006 CS252-s06, Lec 01-intro2Outline• Computer Science at a Crossroads• Computer Architecture v. Instruction Set Arch.• How would you like your CS252?• What Computer Architecture brings to table1/21/2006 CS252-s06, Lec 01-intro3• Old Conventional Wisdom: Power is free, Transistors expensive• New Conventional Wisdom: “Power wall” Power expensive, Xtors free (Can put more on chip than can afford to turn on)• Old CW: Sufficiently increasing Instruction Level Parallelism via compilers, innovation (Out-of-order, speculation, VLIW, …)• New CW: “ILP wall” law of diminishing returns on more HW for ILP • Old CW: Multiplies are slow, Memory access is fast• New CW: “Memory wall” Memory slow, multiplies fast(200 clock cycles to DRAM memory, 4 clocks for multiply)• Old CW: Uniprocessor performance 2X / 1.5 yrs• New CW: Power Wall + ILP Wall + Memory Wall = Brick Wall– Uniprocessor performance now 2X / 5(?) yrs⇒ Sea change in chip design: multiple “cores”(2X processors per chip / ~ 2 years)» More simpler processors are more power efficientCrossroads: Conventional Wisdom in Comp. Arch1/21/2006 CS252-s06, Lec 01-intro41101001000100001978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006Performance (vs. VAX-11/780)25%/year52%/year??%/yearCrossroads: Uniprocessor Performance• VAX : 25%/year 1978 to 1986• RISC + x86: 52%/year 1986 to 2002• RISC + x86: ??%/year 2002 to presentFrom Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 4th edition, October, 20061/21/2006 CS252-s06, Lec 01-intro5Sea Change in Chip Design• Intel 4004 (1971): 4-bit processor,2312 transistors, 0.4 MHz, 10 micron PMOS, 11 mm2 chip • Processor is the new transistor?• RISC II (1983): 32-bit, 5 stage pipeline, 40,760 transistors, 3 MHz, 3 micron NMOS, 60 mm2 chip• 125 mm2 chip, 0.065 micron CMOS = 2312 RISC II+FPU+Icache+Dcache– RISC II shrinks to ~ 0.02 mm2at 65 nm– Caches via DRAM or 1 transistor SRAM (www.t-ram.com) ?– Proximity Communication via capacitive coupling at > 1 TB/s ?(Ivan Sutherland @ Sun / Berkeley)1/21/2006 CS252-s06, Lec 01-intro6Déjà vu all over again?• Multiprocessors imminent in 1970s, ‘80s, ‘90s, …• “… today’s processors … are nearing an impasse as technologies approach the speed of light..”David Mitchell, The Transputer: The Time Is Now (1989)• Transputer was premature ⇒ Custom multiprocessors strove to lead uniprocessors⇒ Procrastination rewarded: 2X seq. perf. / 1.5 years• “We are dedicating all of our future product development to multicore designs. … This is a sea change in computing”Paul Otellini, President, Intel (2004) • Difference is all microprocessor companies switch to multiprocessors (AMD, Intel, IBM, Sun; all new Apples 2 CPUs) ⇒ Procrastination penalized: 2X sequential perf. / 5 yrs⇒ Biggest programming challenge: 1 to 2 CPUs1/21/2006 CS252-s06, Lec 01-intro7Problems with Sea Change • Algorithms, Programming Languages, Compilers, Operating Systems, Architectures, Libraries, … not ready to supply Thread Level Parallelism or Data Level Parallelism for 1000 CPUs / chip, • Architectures not ready for 1000 CPUs / chip• Unlike Instruction Level Parallelism, cannot be solved by just by computer architects and compiler writers alone, but also cannot be solved without participation of computer architects• This edition of CS 252 (and 4thEdition of textbook Computer Architecture: A Quantitative Approach) explores shift from Instruction Level Parallelism to Thread Level Parallelism / Data Level Parallelism1/21/2006 CS252-s06, Lec 01-intro8Outline• Computer Science at a Crossroads• Computer Architecture v. Instruction Set Arch.• How would you like your CS252?• What Computer Architecture brings to table1/21/2006 CS252-s06, Lec 01-intro9Instruction Set Architecture: Critical Interfaceinstruction setsoftwarehardware• Properties of a good abstraction– Lasts through many generations (portability)– Used in many different ways (generality)– Provides convenient functionality to higher levels– Permits an efficient implementation at lower levels1/21/2006 CS252-s06, Lec 01-intro10Example: MIPS0r0r1°°°r31PClohiProgrammable storage2^32 x bytes31 x 32-bit GPRs (R0=0)32 x 32-bit FP regs (paired DP)HI, LO, PCData types ?Format ?Addressing Modes?Arithmetic logical Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUISLL, SRL, SRA, SLLV, SRLV, SRAVMemory AccessLB, LBU, LH, LHU, LW, LWL,LWRSB, SH, SW, SWL, SWRControlJ, JAL, JR, JALRBEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL32-bit instructions on word boundary1/21/2006 CS252-s06, Lec 01-intro11Instruction Set Architecture“... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation.”– Amdahl, Blaauw, and Brooks, 1964SOFTWARESOFTWARE-- Organization of Programmable Storage-- Data Types & Data Structures:Encodings & Representations-- Instruction Formats-- Instruction (or Operation Code) Set-- Modes of Addressing and Accessing Data Items and Instructions-- Exceptional Conditions1/21/2006 CS252-s06, Lec 01-intro12ISA vs. Computer Architecture• Old definition of computer architecture = instruction set design – Other aspects of computer design called implementation – Insinuates implementation is uninteresting or less challenging• Our view is computer architecture >> ISA• Architect’s job much more than instruction set design; technical hurdles today more challenging than those in instruction set design• Since instruction set design not where action is, some conclude computer architecture (using old definition) is not where action is– We disagree on conclusion– Agree that ISA not where action is (ISA in CA:AQA 4/e appendix)1/21/2006 CS252-s06, Lec 01-intro13Comp. Arch. is an Integrated Approach • What really matters is the functioning of the complete system – hardware, runtime system, compiler, operating system, and application– In networking, this is called the “End to End argument”• Computer architecture
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