DOC PREVIEW
Berkeley COMPSCI 252 - Memory Hierarchy—Reducing Hit Time, Main Memory, and Examples

This preview shows page 1-2-3-20-21-40-41-42 out of 42 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 42 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 42 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 42 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 42 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 42 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 42 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 42 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 42 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 42 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

DAP Spr.‘98 ©UCB 1Lecture 11: Memory Hierarchy—Reducing Hit Time, Main Memory, and ExamplesProfessor David A. PattersonComputer Science 252Spring 1998DAP Spr.‘98 ©UCB 2Review: Reducing Misses• 3 Cs: Compulsory, Capacity, Conflict Misses• Reducing Miss Rate1. Reduce Misses via Larger Block Size2. Reduce Misses via Higher Associativity3. Reducing Misses via Victim Cache4. Reducing Misses via Pseudo-Associativity5. Reducing Misses by HW Prefetching Instr, Data6. Reducing Misses by SW Prefetching Data7. Reducing Misses by Compiler Optimizations• Remember danger of concentrating on just one parameter when evaluating performanceCPUtime = IC × CPIExecution+Memory accessesInstruction×Miss rate× Miss penalty    ×Clock cycle timeDAP Spr.‘98 ©UCB 3Reducing Miss Penalty Summary• Five techniques– Read priority over write on miss– Subblock placement– Early Restart and Critical Word First on miss– Non-blocking Caches (Hit under Miss, Miss under Miss)– Second Level Cache• Can be applied recursively to Multilevel Caches– Danger is that time to DRAM will grow with multiple levels in between– First attempts at L2 caches can make things worse, since increased worst case is worse• Out-of-order CPU can hide L1 data cache miss (≈3–5 clocks), but stall on L2 miss (≈40–100 clocks)?CPUtime = IC × CPIExecution+Memory accessesInstruction× Miss rate× Miss penalty    ×Clock cycle timeDAP Spr.‘98 ©UCB 4Review: Improving Cache Performance1. Reduce the miss rate, 2. Reduce the miss penalty, or3. Reduce the time to hit in the cache.DAP Spr.‘98 ©UCB 51. Fast Hit times via Small and Simple Caches• Why Alpha 21164 has 8KB Instruction and 8KB data cache + 96KB second level cache?– Small data cache and clock rate• Direct Mapped, on chipDAP Spr.‘98 ©UCB 62. Fast hits by Avoiding Address Translation• Send virtual address to cache? Called Virtually Addressed Cache or just Virtual Cache vs. Physical Cache– Every time process is switched logically must flush the cache; otherwise get false hits» Cost is time to flush + “compulsory” misses from empty cache– Dealing with aliases (sometimes called synonyms); Two different virtual addresses map to same physical address– I/O must interact with cache, so need virtual address• Solution to aliases– HW guarantees that every cache block has unique physical address– SW guarantee: lower n bits must have same address; as long as covers index field & direct mapped, they must be unique;called page coloring• Solution to cache flush– Add process identifier tag that identifies process as well as address within process: can’t get a hit if wrong processDAP Spr.‘98 ©UCB 7Virtually Addressed CachesCPUTB$MEMVAPAPAConventionalOrganizationCPU$TBMEMVAVAPAVirtually Addressed CacheTranslate only on missSynonym ProblemCPU$ TBMEMVAPATagsPAOverlap $ accesswith VA translation:requires $ index toremain invariantacross translationVATagsL2 $DAP Spr.‘98 ©UCB 82. Fast Cache Hits by Avoiding Translation: Process ID impact• Black is uniprocess• Light Gray is multiprocess when flush cache• Dark Gray is multiprocess when use Process ID tag• Y axis: Miss Rates up to 20%• X axis: Cache size from 2 KB to 1024 KBDAP Spr.‘98 ©UCB 92. Fast Cache Hits by Avoiding Translation Avoiding Translation: Index with Physical Portion of Address• If index is physical part of address, can start tag access in parallel with translation so that can compare to physical tag• Limits cache to page size: what if want bigger caches and uses same trick?– Higher associativity moves barrier to right– Page coloringPage AddressPage OffsetAddress TagIndexBlock OffsetDAP Spr.‘98 ©UCB 10• Pipeline Tag Check and Update Cache as separate stages; current write tag check & previous write cache update • Only STORES in the pipeline; empty during a missStore r2, (r1) Check r1Add --Sub --Store r4, (r3) M[r1]<-r2&check r3• In shade is “Delayed Write Buffer”; must be checked on reads; either complete write or read from buffer3. Fast Hit Times Via Pipelined WritesDAP Spr.‘98 ©UCB 114. Fast Writes on Misses Via Small Subblocks• If most writes are 1 word, subblock size is 1 word, & write through then always write subblock & tag immediately – Tag match and valid bit already set: Writing the block was proper, & nothing lost by setting valid bit on again.– Tag match and valid bit not set: The tag match means that this is the proper block; writing the data into the subblock makes it appropriate to turn the valid bit on.– Tag mismatch: This is a miss and will modify the data portion of the block. Since write-through cache, no harm was done; memory still has an up-to-date copy of the old value. Only the tag to the address of the write and the valid bits of the other subblock need be changed because the valid bit for this subblock has already been set• Doesn’t work with write back due to last caseDAP Spr.‘98 ©UCB 12Cache Optimization SummaryTechnique MR MP HT ComplexityLarger Block Size + – 0Higher Associativity + – 1Victim Caches + 2Pseudo-Associative Caches + 2HW Prefetching of Instr/Data + 2Compiler Controlled Prefetching + 3Compiler Reduce Misses + 0Priority to Read Misses + 1Subblock Placement + + 1Early Restart & Critical Word 1st + 2Non-Blocking Caches + 3Second Level Caches + 2Small & Simple Caches – + 0Avoiding Address Translation + 2Pipelining Writes + 1miss ratehit timemisspenaltyDAP Spr.‘98 ©UCB 13What is the Impact of What You’ve Learned About Caches?• 1960-1985: Speed = ƒ(no. operations)• 1990– Pipelined Execution & Fast Clock Rate– Out-of-Order execution– Superscalar Instruction Issue• 1998: Speed = ƒ(non-cached memory accesses)• What does this mean for– Compilers?,Operating Systems?, Algorithms? Data Structures?1101001000198019811982198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPUDAP Spr.‘98 ©UCB 14Main Memory Background• Performance of Main Memory: – Latency: Cache Miss Penalty» Access Time: time between request and word arrives» Cycle Time: time between requests– Bandwidth: I/O & Large Block Miss Penalty (L2)• Main Memory is DRAM: Dynamic Random Access Memory– Dynamic since needs to be refreshed periodically (8 ms, 1% time)– Addresses divided into 2 halves (Memory as a 2D matrix):» RAS or Row Access Strobe» CAS or Column Access Strobe• Cache uses SRAM: Static Random Access Memory–


View Full Document

Berkeley COMPSCI 252 - Memory Hierarchy—Reducing Hit Time, Main Memory, and Examples

Documents in this Course
Quiz

Quiz

9 pages

Caches I

Caches I

46 pages

Lecture 6

Lecture 6

36 pages

Lecture 9

Lecture 9

52 pages

Figures

Figures

26 pages

Midterm

Midterm

15 pages

Midterm

Midterm

14 pages

Midterm I

Midterm I

15 pages

ECHO

ECHO

25 pages

Quiz  1

Quiz 1

12 pages

Load more
Download Memory Hierarchy—Reducing Hit Time, Main Memory, and Examples
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Memory Hierarchy—Reducing Hit Time, Main Memory, and Examples and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Memory Hierarchy—Reducing Hit Time, Main Memory, and Examples 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?