EECS 252 Graduate Computer Architecture Lec 1 - IntroductionOutlineWhat is “Computer Architecture”?Forces on Computer ArchitectureThe Instruction Set: a Critical InterfaceInstruction Set ArchitectureComputer OrganizationFundamental Execution CycleElements of an ISAExample: MIPS R3000Evolution of Instruction SetsDramatic Technology AdvanceMoore’s LawTechnology Trends: Microprocessor CapacityMemory Capacity (Single Chip DRAM)Technology TrendsPerformance TrendsProcessor Performance (1.35X before, 1.55X now)Definition: PerformanceMetrics of PerformanceComponents of PerformanceWhat’s a Clock Cycle?Integrated ApproachHow do you turn more stuff into more performance?Pipelined Instruction ExecutionLimits to pipeliningA take on Moore’s LawProgression of ILPModern ILPHave we reached the end of ILP?When all else fails - guessCS252: AdminstriviaTypical Class format (after week 2)GradingQuizesThe Memory AbstractionProcessor-DRAM Memory Gap (latency)Levels of the Memory HierarchyThe Principle of LocalityThe Cache Design SpaceIs it all about memory system design?Memory Abstraction and ParallelismSystem Organization: It’s all about communicationBreaking the HW/Software Boundary“Bell’s Law” – new class per decadeIt’s not just about bigger and faster!The Process of DesignAmdahl’s LawComputer Architecture TopicsSlide 50CS 252 Course FocusTopic CoverageYour CS252Research Paper ReadingCoping with CS 252Related CoursesEECS 252 Graduate Computer Architecture Lec 1 - Introduction David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs25201/14/19CS252-s05, Lec 01-intro2Outline•What is Computer Architecture?•Computer Instruction Sets – the fundamental abstraction–review and set up•Dramatic Technology Advance•Beneath the illusion – nothing is as it appears•Computer Architecture Renaissance•How would you like your CS252?01/14/19CS252-s05, Lec 01-intro3What is “Computer Architecture”?ApplicationsInstruction Set ArchitectureCompilerOperatingSystemFirmware•Coordination of many levels of abstraction•Under a rapidly changing set of forces•Design, Measurement, and EvaluationI/O systemInstr. Set Proc.Digital DesignCircuit DesignDatapath & Control Layout & fabSemiconductor MaterialsDie photoApp photo01/14/19CS252-s05, Lec 01-intro4Forces on Computer ArchitectureComputerArchitectureTechnologyProgrammingLanguagesOperatingSystemsHistoryApplications(A = F / M)01/14/19CS252-s05, Lec 01-intro5The Instruction Set: a Critical Interfaceinstruction setsoftwarehardware•Properties of a good abstraction–Lasts through many generations (portability)–Used in many different ways (generality)–Provides convenient functionality to higher levels–Permits an efficient implementation at lower levels01/14/19CS252-s05, Lec 01-intro6Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. – Amdahl, Blaaw, and Brooks, 1964SOFTWARESOFTWARE-- Organization of Programmable Storage-- Data Types & Data Structures: Encodings & Representations-- Instruction Formats-- Instruction (or Operation Code) Set-- Modes of Addressing and Accessing Data Items and Instructions-- Exceptional Conditions01/14/19CS252-s05, Lec 01-intro7Computer OrganizationLogic Designer's ViewISA LevelFUs & Interconnect•Capabilities & Performance Characteristics of Principal Functional Units–(e.g., Registers, ALU, Shifters, Logic Units, ...)•Ways in which these components are interconnected•Information flows between components•Logic and means by which such information flow is controlled.•Choreography of FUs to realize the ISA•Register Transfer Level (RTL) Description01/14/19CS252-s05, Lec 01-intro8Fundamental Execution CycleInstructionFetchInstructionDecodeOperandFetchExecuteResultStoreNextInstructionObtain instruction from program storageDetermine required actions and instruction sizeLocate and obtain operand dataCompute result value or statusDeposit results in storage for later useDetermine successor instructionProcessorregsF.U.sMemoryprogramDatavon Neumanbottleneck01/14/19CS252-s05, Lec 01-intro9Elements of an ISA•Set of machine-recognized data types–bytes, words, integers, floating point, strings, . . .•Operations performed on those data types–Add, sub, mul, div, xor, move, ….•Programmable storage–regs, PC, memory•Methods of identifying and obtaining data referenced by instructions (addressing modes)–Literal, reg., absolute, relative, reg + offset, …•Format (encoding) of the instructions–Op code, operand fields, …Current Logical Stateof the MachineNext Logical Stateof the Machine01/14/19CS252-s05, Lec 01-intro10Example: MIPS R30000r0r1°°°r31PClohiProgrammable storage2^32 x bytes31 x 32-bit GPRs (R0=0)32 x 32-bit FP regs (paired DP)HI, LO, PCData types ?Format ?Addressing Modes?Arithmetic logical Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUISLL, SRL, SRA, SLLV, SRLV, SRAVMemory AccessLB, LBU, LH, LHU, LW, LWL,LWRSB, SH, SW, SWL, SWRControlJ, JAL, JR, JALRBEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL32-bit instructions on word boundary01/14/19CS252-s05, Lec 01-intro11Evolution of Instruction SetsSingle Accumulator (EDSAC 1950)Accumulator + Index Registers(Manchester Mark I, IBM 700 series 1953)Separation of Programming Model from ImplementationHigh-level Language Based (Stack) Concept of a Family(B5000 1963) (IBM 360 1964)General Purpose Register MachinesComplex Instruction Sets Load/Store ArchitectureRISC(Vax, Intel 432 1977-80)(CDC 6600, Cray 1 1963-76)(MIPS,Sparc,HP-PA,IBM RS6000, 1987)iX86?01/14/19CS252-s05, Lec 01-intro12Dramatic Technology Advance•Prehistory: Generations–1st Tubes–2nd Transistors–3rd Integrated Circuits–4th VLSI….•Discrete advances in each generation–Faster, smaller, more reliable, easier to utilize•Modern computing: Moore’s Law–Continuous advance, fairly homogeneous technology01/14/19CS252-s05, Lec 01-intro13Moore’s Law•“Cramming More Components onto Integrated Circuits”–Gordon Moore, Electronics, 1965•# on transistors on cost-effective integrated circuit double every 18 months01/14/19CS252-s05, Lec
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