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Berkeley COMPSCI 252 - Breaking Processors for Increased Performance & Reduced Power Consumption

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AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionBackgroundBackground / MotivationMotivationSlide 5Slide 6Proposal: AVIDAVID!More AVIDMethodologyComparisonResults: CPI in Best CaseResults: Power ConsumptionConclusionsFuture WorkQuestions?AVID: Breaking Processors AVID: Breaking Processors for Increased Performance for Increased Performance & Reduced Power & Reduced Power ConsumptionConsumptionDouglas Lacy & Daniel LeCheminantDouglas Lacy & Daniel LeCheminantCS 252CS 252December 10, 2003December 10, 200322AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionBackgroundBackgroundTodd Austin’s DIVA paperTodd Austin’s DIVA paperDIVA dynamically verifies all instructions, DIVA dynamically verifies all instructions, guarding against transient and permanent guarding against transient and permanent faultsfaultsAustin speculated that DIVA could allow Austin speculated that DIVA could allow throttling of processor clock speedthrottling of processor clock speed33AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionBackground / MotivationBackground / MotivationDIVA: maintains correctness even with DIVA: maintains correctness even with malfunctioning hardwaremalfunctioning hardwareIs there a way to “break” the core Is there a way to “break” the core processor in such a way as to optimize it?processor in such a way as to optimize it?Remove rarely-used components?Remove rarely-used components?Reduce tolerance in clock cycle, voltage, etc?Reduce tolerance in clock cycle, voltage, etc?May be possible to dynamically alter May be possible to dynamically alter processor to be only as correct as necessaryprocessor to be only as correct as necessary44AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionMotivationMotivationSome components of processors exist to Some components of processors exist to ensure correctness in rarer casesensure correctness in rarer casesMay waste resources and cycles to check May waste resources and cycles to check these casesthese casesWith DIVA, we can ignore them, mostlyWith DIVA, we can ignore them, mostly““Rare” is variableRare” is variableCould be lazy with some computations, need Could be lazy with some computations, need to be more strict with othersto be more strict with othersWhich are possible is dependent on programWhich are possible is dependent on program55AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionMotivationMotivationcc1cc1anagramanagramcompresscompress% Loads% Loads23%23%24%24%21%21%% Stores% Stores14%14%10%10%14%14%% Loads/% Loads/StoresStores37%37%33%33%36%36%66AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionMotivationMotivationSpecifically, what can we remove/throttle?Specifically, what can we remove/throttle?Memory disambiguationMemory disambiguationBranch predictionBranch predictionBranch checkingBranch checkingExceptionsExceptionsLong-latency operations (multiply & divide)Long-latency operations (multiply & divide)Rare instructions?Rare instructions?PrefetchingPrefetching77AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionProposal: AVIDProposal: AVIDAVID: Architecture that Varies, Input AVID: Architecture that Varies, Input DependentDependentUse a DIVA unit to provide verification, Use a DIVA unit to provide verification, and also feedback to the core processorand also feedback to the core processorCan dynamically throttle operations from Can dynamically throttle operations from most time/power-consuming and correct to most time/power-consuming and correct to least consuming and sometimes incorrectleast consuming and sometimes incorrectWon’t require much more hardware than Won’t require much more hardware than standard DIVAstandard DIVA88AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID!AVID!99AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionMore AVIDMore AVIDBranch predictorsBranch predictorsStatic, bimodal, 2-level, hybridStatic, bimodal, 2-level, hybridMultiply/DivideMultiply/DivideTruncate inputs, run for fewer cyclesTruncate inputs, run for fewer cyclesLoadsLoadsAllow them to proceed past unresolved storesAllow them to proceed past unresolved storesClock cycle throttlingClock cycle throttlingStart fast, reduce speed if errors crop upStart fast, reduce speed if errors crop up1010AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionMethodologyMethodologySimulate in SimpleScalarSimulate in SimpleScalarBase architecture: Standard DIVABase architecture: Standard DIVAModify simple scalar to include a core & Modify simple scalar to include a core & DIVA unitDIVA unitModify base architecture into AVIDModify base architecture into AVIDDIVA catches all errors so processor is still DIVA catches all errors so processor is still functional & reliablefunctional & reliable1111AVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionAVID: Breaking Processors for Increased Performance & Reduced Power ConsumptionRun benchmarks on both architectures & Run benchmarks on both architectures & compare performance (SPEC or similar)compare performance (SPEC or similar)CPI: Read from simulator outputCPI: Read from simulator outputExec. Time: Total cycles * cycle timeExec. Time: Total cycles * cycle timePower ConsumptionPower ConsumptionTotal cycles * constant + Total cycles * constant + branch predictions * constant for type of pred.branch predictions * constant for type of pred.Amount of hardwareAmount of hardwareComparisonComparison1212AVID: Breaking Processors for Increased


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Berkeley COMPSCI 252 - Breaking Processors for Increased Performance & Reduced Power Consumption

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