EECS 252 Graduate Computer Architecture Lec 23 – Storage TechnologyClassical DRAM Organization (square)Review:1-T Memory Cell (DRAM)DRAM Capacitors: more capacitance in a small areaDRAM Read Timing4 Key DRAM Timing ParametersMain Memory PerformanceIncreasing Bandwidth - InterleavingSlide 9Slide 10Avoiding Bank ConflictsFinding Bank Number and Address within a bankSlide 13Fast Bank NumberFast Memory Systems: DRAM specificFast Page Mode OperationDRAM HistoryDRAM Future: 1 Gbit+ DRAMDRAMs per PC over TimePotential DRAM Crossroads?Something new: Structure of Tunneling Magnetic JunctionMEMS-based StorageBig storage (such as DRAM/DISK): Potential for Errors!General Idea: Code Vector SpaceError Correction Codes (ECC)Correcting Code ConceptSimple Error Detection CodingHamming Error Correcting CodeHamming Code ExampleInteractive QuizReview: Hamming Error Correcting CodeReview: Code TypesMotivation: Who Cares About I/O?I/O SystemsTechnology TrendsStorage Technology DriversHistorical PerspectiveDisk HistorySlide 39Slide 40MBits per square inch: DRAM as % of Disk over timeDisk Performance Model /TrendsPhoto of Disk Head, Arm, ActuatorNano-layered Disk HeadsDisk Device TerminologyDisk Performance ExampleDisk Time ExampleSnapshot: Ultrastar 72ZXWhat Kind of ErrorsConcept: Redundant CheckExample: TCP ChecksumExample: Ethernet CRC-32CRC conceptGalois Fields - the theory behind LFSRsGalois Fields - The theory behind LFSRsSo what about division (mod)Polynomial divisionCRC encodingCRC decodingSlide 60Galois Fields – PrimitivesPrimitive PolynomialsBuilding an LFSR from a Primitive PolyGenerating PolynomialsAlternative Data Storage Technologies: Early 1990sTape vs. DiskCurrent Drawbacks to TapeAutomated Cartridge SystemRelative Cost of Storage Technology—Late 1995/Early 1996Manufacturing Advantages of Disk ArraysReplace Small # of Large Disks with Large # of Small Disks! (1988 Disks)Array ReliabilityRedundant Arrays of DisksRedundant Arrays of Disks RAID 1: Disk Mirroring/ShadowingRedundant Arrays of Disks RAID 3: Parity DiskRedundant Arrays of Disks RAID 5+: High I/O Rate ParityProblems of Disk Arrays: Small WritesSubsystem OrganizationSystem Availability: Orthogonal RAIDsSystem-Level AvailabilitySummaryEECS 252 Graduate Computer Architecture Lec 23 – Storage Technology David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs252Classical DRAM Organization (square)rowdecoderrowaddressColumn Selector & I/O CircuitsColumnAddressdataRAM Cell Arrayword (row) selectbit (data) lines•Row and Column Address together: –Select 1 bit a timeEach intersection representsa 1-T DRAM CellReview:1-T Memory Cell (DRAM)•Write:–1. Drive bit line–2.. Select row•Read:–1. Precharge bit line to Vdd/2–2.. Select row–3. Cell and bit line share charges»Very small voltage changes on the bit line–4. Sense (fancy sense amp)»Can detect changes of ~1 million electrons–5. Write: restore the value •Refresh–1. Just do a dummy read to every cell.row selectbitDRAM Capacitors: more capacitance in a small area•Trench capacitors:–Logic ABOVE capacitor–Gain in surface area of capacitor–Better Scaling properties–Better Planarization•Stacked capacitors–Logic BELOW capacitor–Gain in surface area of capacitor–2-dim cross-section quite smallADOE_L256K x 8DRAM9 8WE_LCAS_LRAS_LOE_LA Row AddressWE_LJunkRead AccessTimeOutput EnableDelayCAS_LRAS_LCol Address Row Address JunkCol AddressD High Z Data OutDRAM Read Cycle TimeEarly Read Cycle: OE_L asserted before CAS_L Late Read Cycle: OE_L asserted after CAS_L•Every DRAM access begins at:–The assertion of the RAS_L–2 ways to read: early or late v. CAS Junk Data Out High ZDRAM Read Timing4 Key DRAM Timing Parameters•tRAC: minimum time from RAS line falling to the valid data output. –Quoted as the speed of a DRAM when buy–A typical 4Mb DRAM tRAC = 60 ns–Speed of DRAM since on purchase sheet?•tRC: minimum time from the start of one row access to the start of the next. –tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns•tCAC: minimum time from CAS line falling to valid data output. –15 ns for a 4Mbit DRAM with a tRAC of 60 ns•tPC: minimum time from the start of one column access to the start of the next. –35 ns for a 4Mbit DRAM with a tRAC of 60 ns•DRAM (Read/Write) Cycle Time >> DRAM (Read/Write) Access Time– 2:1; why?•DRAM (Read/Write) Cycle Time :–How frequent can you initiate an access?–Analogy: A little kid can only ask his father for money on Saturday•DRAM (Read/Write) Access Time:–How quickly will you get what you want once you initiate an access?–Analogy: As soon as he asks, his father will give him the money •DRAM Bandwidth Limitation analogy:–What happens if he runs out of money on Wednesday?TimeAccess TimeCycle TimeMain Memory PerformanceAccess Pattern without Interleaving:Start Access for D1CPU MemoryStart Access for D2D1 availableAccess Pattern with 4-way Interleaving:Access Bank 0Access Bank 1Access Bank 2Access Bank 3We can Access Bank 0 againCPUMemoryBank 1MemoryBank 0MemoryBank 3MemoryBank 2Increasing Bandwidth - Interleaving•Simple: –CPU, Cache, Bus, Memory same width (32 bits)•Interleaved: –CPU, Cache, Bus 1 word: Memory N Modules(4 Modules); example is word interleaved•Wide: –CPU/Mux 1 word; Mux/Cache, Bus, Memory N words (Alpha: 64 bits & 256 bits)Main Memory Performance•Timing model–1 to send address, –4 for access time, 10 cycle time, 1 to send data–Cache Block is 4 words•Simple M.P. = 4 x (1+10+1) = 48•Wide M.P. = 1 + 10 + 1 = 12•Interleaved M.P. = 1+10+1 + 3 =15addressBank 004812addressBank 115913addressBank 2261014addressBank 3371115Main Memory PerformanceAvoiding Bank Conflicts•Lots of banksint x[256][512];for (j = 0; j < 512; j = j+1)for (i = 0; i < 256; i = i+1)x[i][j] = 2 * x[i][j];•Even with 128 banks, since 512 is multiple of 128, conflict on word accesses•SW: loop interchange or declaring array not power of 2 (“array padding”)•HW: Prime number of banks–bank number = address mod number of banks–bank number = address mod number of banks–address within bank = address / number of words in bank–modulo & divide per memory access with prime no. banks?Finding Bank Number and Address within a bankProblem: We want to determine the number of banks, Nb, to useand the number of words to store in each
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