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Berkeley COMPSCI 252 - Lecture 1 Introduction

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Page 1CS252/CullerLec 1. 11/22/02January 22, 2002Prof. David E CullerComputer Science 252Spring 2002CS252Graduate Computer ArchitectureLecture 1IntroductionCS252/CullerLec 1. 21/22/02Outline• Why Take CS252?• Fundamental Abstractions & Concepts• Instruction Set Architecture & Organization• Administrivia• Pipelined Instruction Processing• Performance• The Memory Abstraction• SummaryCS252/CullerLec 1. 31/22/02Why take CS252?• To design the next great instruction set?...well...– instruction set architecture has largely converged– especially in the desktop / server / laptop space– dictated by powerful market forces• Tremendous organizational innovation relative to established ISA abstractions• Many New instruction sets or equivalent– embedded space, controllers, specialized devices, ...• Design, analysis, implementation concepts vital to all aspects of EE & CS– systems, PL, theory, circuit design, VLSI, comm.• Equip you with an intellectual toolbox for dealing with a host of systems design challengesCS252/CullerLec 1. 41/22/02Example Hot Developments ca. 2002• Manipulating the instruction set abstraction– itanium: translate ISA64 -> micro-op sequences– transmeta: continuous dynamic translation of IA32– tinsilica: synthesize the ISA from the application– reconfigurable HW• Virtualization– vmware: emulate full virtual machine– JIT: compile to abstract virtual machine, dynamically compile to host• Parallelism– wide issue, dynamic instruction scheduling, EPIC– multithreading (SMT)– chip multiprocessors• Communication– network processors, network interfaces• Exotic explorations– nanotechnology, quantum computingCS252/CullerLec 1. 51/22/02Forces on Computer ArchitectureComputerArchitectureTechnology ProgrammingLanguagesOperatingSystemsHistoryApplications(A = F / M)CS252/CullerLec 1. 61/22/02Amazing Underlying Technology ChangePage 2CS252/CullerLec 1. 71/22/02A take on Moore’s LawTransistorsuuuuuuuuuuuuuuuuuuuuuuuuuu uuuuuu uuuuuuuuuuuuuuuu uuu uuuuuuu uuuuuu uuu1,00010,000100,0001,000,00010,000,000100,000,0001970 1975 1980 1985 1990 1995 2000 2005Bit-level parallelism Instruction-level Thread-level (?)i4004i8008i8080i8086i80286i80386R2000Pentium R10000R3000CS252/CullerLec 1. 81/22/02Technology Trends• Clock Rate: ~30% per year• Transistor Density: ~35%• Chip Area: ~15%• Transistors per chip: ~55%• Total Performance Capability: ~100%• by the time you graduate...– 3x clock rate (3-4 GHz)– 10x transistor count (1 Billion transistors)– 30x raw capability• plus 16x dram density, 32x disk densityCS252/CullerLec 1. 91/22/02Performance0.11101001965 1970 1975 1980 1985 1990 1995SupercomputersMinicomputersMainframesMicroprocessorsPerformance TrendsCS252/CullerLec 1. 101/22/02Measurement and EvaluationArchitecture is an iterative process-- searching the space of possible designs-- at all levels of computer systemsGood IdeasGood IdeasMediocre IdeasBad IdeasCost /PerformanceAnalysisDesignAnalysisCreativityCS252/CullerLec 1. 111/22/02What is “Computer Architecture”?I/O systemInstr. Set Proc.CompilerOperatingSystemApplicationDigital DesignCircuit DesignInstruction SetArchitectureFirmware• Coordination of many levels of abstraction• Under a rapidly changing set of forces• Design, Measurement, and EvaluationDatapath & Control LayoutCS252/CullerLec 1. 121/22/02Coping with CS 252• Students with too varied background?– In past, CS grad students took written prelim exams on undergraduate material in hardware, software, and theory– 1st 5 weeks reviewed background, helped 252, 262, 270– Prelims were dropped => some unprepared for CS 252?• In class exam on Tues Jan. 29 (30 mins)– Doesn’t affect grade, only admission into class– 2 grades: Admitted or audit/take CS 152 1st– Improve your experience if recapture common background• Review: Chapters 1, CS 152 home page, maybe “Computer Organization and Design (COD)2/e” – Chapters 1 to 8 of COD if never took prerequisite– If took a class, be sure COD Chapters 2, 6, 7 are familiar– Copies in Bechtel Library on 2-hour reserve• FAST review this week of basic conceptsPage 3CS252/CullerLec 1. 131/22/02Review of Fundamental Concepts• Instruction Set Architecture• Machine Organization• Instruction Execution Cycle• Pipelining• Memory• Bus (Peripheral Hierarchy)• Performance Iron TriangleCS252/CullerLec 1. 141/22/02The Instruction Set: a Critical Interfaceinstruction setsoftwarehardwareCS252/CullerLec 1. 151/22/02Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. – Amdahl, Blaaw, and Brooks, 1964SOFTWARESOFTWARE-- Organization of Programmable Storage-- Data Types & Data Structures:Encodings & Representations-- Instruction Formats-- Instruction (or Operation Code) Set-- Modes of Addressing and Accessing Data Items and Instructions-- Exceptional ConditionsCS252/CullerLec 1. 161/22/02OrganizationLogic Designer's ViewISA LevelFUs & Interconnect• Capabilities & Performance Characteristics of Principal Functional Units– (e.g., Registers, ALU, Shifters, Logic Units, ...)• Ways in which these components are interconnected• Information flows between components• Logic and means by which such information flow is controlled.• Choreography of FUs to realize the ISA• Register Transfer Level (RTL) DescriptionCS252/CullerLec 1. 171/22/02Review: MIPS R3000 (core)0r0r1°°°r31PClohiProgrammable storage2^32 x bytes31 x 32-bit GPRs (R0=0)32 x 32-bit FP regs (paired DP)HI, LO, PCData types ?Format ?Addressing Modes?Arithmetic logical Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU,AddI , AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUISLL, SRL, SRA, SLLV, SRLV, SRAVMemory AccessLB, LBU, LH, LHU, LW, LWL,LWRSB, SH, SW, SWL, SWRControlJ, JAL, JR, JALRBEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL32-bit instructions on word boundaryCS252/CullerLec 1. 181/22/02Review: Basic ISA ClassesAccumulator:1 address add A acc ← acc + mem[A]1+x address addx A acc ← acc + mem[A + x]Stack:0 address add tos ← tos + nextGeneral Purpose Register:2 address add A B EA(A) ← EA(A) + EA(B)3 address add A B C EA(A) ← EA(B) + EA(C)Load/Store:3 address add Ra Rb Rc Ra ← Rb + Rcload Ra Rb Ra ← mem[Rb]store Ra Rb mem[Rb] ←


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Berkeley COMPSCI 252 - Lecture 1 Introduction

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