Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6 002 Electronic Circuits Spring 2000 Homework 4 Issued 2 23 2000 Due 3 1 2000 Exercise 4 1 Demonstrate de Morgan s Theorem which states that A B A B and that A B A B where A and B are Boolean variables Exercise 4 2 First using only NOT gates and two input NAND gates construct a two input AND gate a two input OR gate and a two input NOR gate Second using only NOT gates and twoinput NOR gates construct a two input OR gate a two input AND gate and a two input NAND gate Hint see Exercise 4 1 Exercise 4 3 Using a small number of MOSFETs and pull up resistors construct a three input AND gate and a three input OR gate Problem 4 1 This problem examines the operation and design of the digital logic circuit shown below It is constructed with two identical pull up resistors and four identical MOSFETs and it implements the Boolean expression OUT IN1 IN2 IN3 Assume that each MOSFET behaves as a switch with threshold voltage VT and on state resistance RON A Assume that the logic circuit functions properly For each of the eight input logic value combinations determine the state ON or OFF of the four MOSFETs M1 M2 M3 and M4 the output logic value and the voltages at the gate and drain of M4 Organize the results in a table having ten columns the three input logic values the output logic value the four MOSFET states and the two voltages B Based on the results of Part A what inequalities must VT satisfy so that the voltage at the gate of M4 produces the desired state of M4 C Based on the results of Part A what voltage inequalities must be satisfied so that the output voltage at the drain of M4 satisfies the static discipline defined by VH and VL D Assume that the voltages at the three inputs IN1 IN2 and IN3 satisfy the static discipline defined by VH and VL Based on the results of Part A what voltage inequalities must VT satisfy so that the three input voltages produce the desired states of M1 M2 and M3 E Organize the inequalities into a minimal string of inequalities that must be satisfied in order for the digital circuit to function properly and conform to the static discipline F Assuming that the logic circuit is designed according to the results of Part E determine which combinations of input logic values lead to the maximum and minimum power dissipation in the logic circuit VS RPU RPU OUT M4 IN1 M1 IN2 M2 IN3 M3 Problem 4 2 This problem studies the operation of digital logic circuits constructed from p channel MOSFETs The p channel MOSFET is the complement or mirror image the n channel MOSFET Its symbol and terminal definition are given below When used in a logic circuit it functions as a switch that is ON if vOUT VT and OFF if vGS VT where VT is a negative valued threshold voltage When ON the p channel MOSFET passes current from its source to its drain Derive a Boolean expression that describes the operation of each digital logic circuit shown below Assume that the MOSFETs behave as ideal switches with 0 VT VS and that the logic values 0 and 1 are represented by the voltages 0 V and VS respectively Circuit A Circuit B Circuit C p channel MOSFET VS S G D IN1 VS VS S D IN1 S S D D IN1 IN2 OUT IN2 OUT S D S D OUT Problem 4 3 Determine the Thevenin equivalent of each network shown below Note that these networks contain dependent sources Network A Network B Network C R v i v i R I R1 i R2 i Problem 4 4 This problem studies the two amplifiers shown below Amplifier A is a singlestage amplifier implemented with a voltage dependent current source and a pull up resistor Assume that the current source parameters G and VT satisfy G 0 and VS VT 0 Amplifier B is a two stage amplifier in which each stage is identical to Amplifier A A Determine vOUT as a function of vIN for Amplifier A B Sketch and clearly label a graph of the input output relation found in Part A C Determine vOUT as a function of vIN for Amplifier B D Sketch and clearly label a graph of the input output relation found in Part C E Consider Amplifier A again Show that the dependent current source sinks power for vOUT 0 and sources power for vOUT 0 F Dependent current sources are most often implemented with transistors that are passive devices and hence not capable of sourcing power In this case the dependent current source in Amplifier A would saturate so that vOUT actually never goes below 0 V That is the current through the dependent current source becomes constant and does not increase with a further increase in vA once the voltage across the source reaches 0 V Given this revised behavior for Amplifier A sketch and clearly label a graph of the input output behavior of Amplifier B for very large G Amplifier B Amplifier A VS R vin vA v vout in 0 for vA VT G vin VT for vA VT Amplifier A Amplifier A vout
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