Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.002 – Circuits & ElectronicsSpring 2006Problem Set #7Issued 3/22/06 – Due 4/5/06Exercise 7.1: Each network shown below has a non-zero initial state at t = 0, as indicated.Find the network states for t ≥ 0. Hint: what equivalent resistance is in parallel with each capacitoror inductor, and what decay time results from this combination?R1+ v(t) −CR2v(0) = VR1+v(t)−CR2v(0) = VR1i(t)LR2i(0) = IR1i(t)LR2i(0) = IExercise 7.2: The network shown below contains a voltage source having amplitude V, anideal switch, a 2-kΩ resistor and a capacitor having capacitance C, all in series. At t = 0 the switchcloses, after which the capacitor voltage vCis measured as shown below. From the measuredvoltage, determine V , C, and the capacitor voltage before the switch closed. Note: the last pageof this problem set contains a larger graph of the capacitor voltage. It can be turned in with yourproblem set solutions.V2kΩ− vC(t)+C0 1 2 3 4 5 6 7 8 9 10012345678910Time [ms]Capacitor Voltage [V]Capacitor VoltageProblem 7.1: This problem examines the relation between transient responses of linearsystems. The network shown below is first driven by a current step at t =0,thendrivenbyacurrent ramp at t = 0, and finally driven by the current step plus the current ramp at t =0. Inthe first two cases, the inductor has zero initial current, as indicated.(A) Find the inductor current i(t)fort ≥ 0 in response to the current step I(t)=I◦u−1(t). Assumethat i(0) = 0.(B) Find the inductor current i(t)fort ≥ 0 in response to the current ramp I(t)=I◦αtu−1(t).Again assume that i(0) = 0.(C) The step input can be constructed from the ramp input according to IStep(t)=1αddtIRamp(t).Show that their respective responses are related in a similar manner.(D) Would the result from Part C hold if i(0) = 0? Why or why not?(E) Finally, find the inductor current i(t)fort ≥ 0 in response to the current step plus the currentramp, that is, in response to I(t)=I◦(1 + αt)fort ≥ 0. This time assume that i(0) = i◦.Hint: think superposition.I(t)iLLRProblem 7.2: The circuit shown below can be used to regulate the current through aninductor. (The switches model transistors.) Typical applications include the regulation of currentsin motors, solenoids and loud speakers, all of which have inductive windings. We will analyze thecircuit assuming that it operates in a cyclic manner with switching period T . During the first partof each period, which lasts for a duration DT , switches S1 and S4 are on while switches S2 andS3 are off. During the second part of each switching period, which lasts for a duration (1 − D)T ,switches S1 and S4 are off while switches S2 and S3 are on. Note that 0 ≤ D ≤ 1.(A) Assume that D is constant and that the circuit has been operating long enough to reach acyclic steady state by t = 0, at which point a new switching period begins. In terms of theunknown i(0), determine i(t) for 0 ≤ t ≤ T .(B) Use your result from Part (A), and the fact that the circuit operates in a cyclic steady stateto determine i(0). Note that with this result, and that from Part (A), i(t) is completelydetermined.(C) Find the average value of i(t) over the period 0 ≤ t ≤ T . Hint: is it necessary to average theresult from Part A, or is there a faster method to find the average?(D) Suppose that the circuit has been operating with D ≡ D1for a time long enough to reach acyclic steady state by t = 0. Suppose that D switches to D = D2at t = 0, just as a newswitching period begins. In this case, determine i(t)fort ≥ 0. Hint: can you use your resultfrom Parts (A) and (B) as a particular solution over the interval 0 ≤ t?VS3S4S2S1Ri(t)LProblem 7.3: Consider the digital logic circuit from Problem 3.2. Model each MOSFET witha switch-resistor model having on-state resistance RON. Assume that all pull-up resistors have thesame resistance RPU, and that the resistors satisfy RON RPU.(A) Assume that the inputs IN1, IN2 and IN3 cycle through the eight combinations 000, 001, 010,011, 100, 101, 110, and 111, in order. Assume further that each input combination is held forthe same period T . Under these assumptions, determine the average static power dissipatedby the logic circuit; do so analytically, rather than using the numerical device values givenin Problem 3.2. Make appropriate simplifications based on the inequality for RONand RPU.Hint: see your solutions to Problem 3.2.(B) Assume now that MOSFETs M3 and M4 have the same gate-to-source capacitance CGS.As-sume further that each input combination described above is held for the period T such thatT RPUCGS. Under these assumptions, determine the average dynamic power dissipated bythe logic circuit. Make appropriate simplifications based on the inequalities for RON, RPU,CGSand T .(C) Which is greater, the average static dissipation or the average dynamic dissipation? Hint:make use of the inequalities for RON, RPU, CGSand T .Problem 7.4: The network shown below contains a 0.1-µF capacitor and a 40-µH inductor.At t = 0, the capacitor voltage vCis 5 V, and the inductor current iLis 100 mA.(A) Over what period do the network states oscillate?(B) What is the maximum value that vCwill reach?(C) What is the maximum value that iLwill reach?(D) At what time after t = 0 will vCfirst reach its maximum positive value?(E) At what time after t = 0 will iLfirst reach its maximum positive value?0.1 µFiL40 µH+vC−0 1 2 3 4 5 6 7 8 9 10012345678910Time [ms]Capacitor Voltage [V]Capacitor
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