MASSACHUSETTS INSTITUTE OF TECHNOLOGYDepartment of Electrical Engineering and Computer Science6.002 – Electronic CircuitsFall 2002Quiz 2 SolutionsName:Recitation Section:Recitation Instructor: Teaching Assistant:Enter all your work and your answers directly in the spaces provided on theprinted pages. Make sure that your name is on all sheets. Use the backs of theprinted pages as scratch paper, but we will only grade the work that you neatly transferto the spaces on the printed pages. Answers must be derived or explained, not just simplywritten down. The quiz is closed book, but calculators are allowed.This quiz contains 8 pages including the cover sheet. Make sure that your quiz contains all8 pages and that you hand in all 8 pages.Problem Points Grade Grader1 502 50Total 100Name: Solutions 2Problem 1: (50 points) Figure 1(a) shows a simple one-stage MOSFET amplifier. The input-output relationship is graphed in Figure 1(b), where the solid curve indicates operation in thesaturated region and the dashed curves indicate operation in the cutoff and triode regions.Figure 1: Circuit and characteristic for Problem 1(A) Determine the MOSFET threshold voltage VTand the power supply voltage VS.VT=2VVS=12V(B) Determine the MOSFET parameter K.vO= VS− RLK/2(vI− VT)2=12V − 103Ω · K(vI− 2V )2Using point vI=4V , vO=2V2V =12V − 103Ω · K(4V − 2V )2⇒ K =2.5mA/V2K =2.5mA/V2(C) Determine the minimum and maximum small-signal gain |vovi| in the saturated region. Agraphical solution is acceptable.vovi= RLK(vI− VT)=5V−1(vI− 2V )If vI∈ [2, 4] thenvovi∈ [0, 10]min |vovi| =0max |vovi| =10Name: Solutions 3The circuit shown in Figure 2 is used to bias the amplifier and inject an input signal to beamplified. The values of R1and R2are to be determined.Figure 2: Circuit for Problem 1(D), where vO= VO+ vo(D) Determine the bias voltage EI(with respect to ground) such that equal positive and negativeexcursions of vocan be as large as possible without leaving the saturation region.For maximum excursions, center VOin the middle of the saturation region, i.e., VO=7V .With vi=0V (since it is small-signal and we’re computing bias conditions),choose EIsuch that VO=7V .7V =12V − 5/2V−1(EI− 2V )2⇒ EI=(2+√2)V ≈ 3.4VEI=3.4V(E) The resistors in Figure 2 satisfy the constraint R1+ R2=10kΩ. Determine values for R1andR2so that the bias voltage EIwill be that found in part (D).EI=R2R1+ R25V −R1R1+ R25V =5V10kΩ(R2− R1)R2− R1=(4+2√2)kΩR1+ R2=10kΩ⇒ R1=(3−√2)kΩ ≈ 1.6kΩ⇒ R2=(7+√2)kΩ ≈ 8.4kΩR1=1.6kΩR2=8.4kΩName: Solutions 4(F) Draw the small-signal circuit valid for the operating point defined in part (D). Label thenumerical values of all circuit parameters and determine the small-signal gain at this operatingpoint from your circuit.gm=idvgs=∂iD∂vGSvGS=EI= K(EI− VT)=2.5mA/V2[(2 +√2)V − 2V ]=5√22m✵ ≈ 3.5m✵Gain:vovi= −2kΩ ·5√22m✵ = −5√2m✵ ≈−7vovi=5√2m✵ ≈ 7Name: Solutions 5Problem 2: (50 points) The circuit of Figure 3 is a model for a proposed logic inverter which isto join a logic family whose members must satisfy the following digital discipline:VIH=3.3VVOH=4.0VVIL=1.55VVOL=1.0VFigure 3: Circuit for Problem 2Switch S is controlled by the voltage vINsuchthatitisopenwhenvIN≤ 1.8V and closed otherwise.Also, IS=0.5mA in the current source.(A) Fill in the following table with the output voltages which will result if the circuit is suppliedby input voltages which satisfy the digital discipline:Input vOUT(V )High 0VLow 5VIf vIN<vIL=1.55V thenswitchSisopenandvOUT=0.5mA × 10kΩ=5V .If vIN>vIH=3.3V then switch S is closed, the output terminal is shorted and vOUT=0V .Name: Solutions 6(B) Each gate in this logic family will have the same input resistance RIN. One of the requirementsof this gate is that it be able to drive up to three other gates from this family, connected inparallel. Find the minimum allowable value of RIN, Rmin, such that this gate will satisfy thedigital discipline under all acceptable operating configurations.The constraint is (Rmin/3||10kΩ) × IS= VOH.⇒ Rmin= 120kΩRmin= 120kΩ(C) What is the noise margin for this logic family (i.e., what is the maximum noise amplitude inV that can appear anywhere in a circuit in which this logic family is used such that all thegates in this circuit are guaranteed to operate properly)?Noise margin = min{VIL− VOL,VOH− VIH}=min{1.55V − 1.0V,4.0V − 3.3V }=min{0.55V,0.7V }=0.55VNoise margin = 0.55VName: Solutions 7(D) Circle the logic expressions which describe the logic functions implemented by the circuitsshown in Figures 4 and 5 from the respective lists below each figure. The circuits employthe logic inverter of Figure 3 (indicated by a rectangular box). You may assume that eachMOSFET has threshold voltage, VT,of2.0V .Figure 4: Logic circuit for Problem 2(D)z = xy z =¯x¯y z = x + y z = x + yz = yz=¯x + xy z =¯xy z = x¯x¯y = x + yName: Solutions 8Figure 5: Logic circuit for Problem 2(D)z = xy z =¯x¯yz= x + yz= x + yz = yz=¯x + xy z =¯xyz = x¯x(¯x
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