Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.002 – Circuits & ElectronicsSpring 2004Quiz #21 April 2004Name:• Please put your name in the space provided above, and circle the name of yourrecitation instructor together with the time of your recitation.• Do your work for each question within the boundaries of the question. When finished,write your answer to each question in the corresponding answer box that follows thequestion.• This is a closed-book quiz, but calculators are allowed.• Graded quizzes will b e returned in recitation on Wednesday April 7. If you do notattend recitation on that day, then it is your responsibility to get your quiz fromyour recitation instructor. You will have until recitation on Wednesday April 21 torequest a quiz grading review, regardless of whether or not you attend recitation onWednesday April 7 and take back your quiz. If you wish to have your quiz gradereviewed, you must return your quiz to your recitation instructor, within the twoweek period, together with a written explanation of why you think a grading mistakewas made. This is the only way in which a quiz grade will be reviewed.• Good luck!Problem 1 Problem 2 Problem 3 Total GradeCite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].Problem 1 – 35%A hypothetical “leaky” MOSFET (L-MOSFET) is modeled with the additional gate-to-source resistance RGSas shown below. Also shown below is an inverter constructed usingthe L-MOSFET. Assume that the inverter drives N identical inverters from its output, asindicated. Given this load, the inverter is required to obey the standard static disciplinedefined by 0 <VOL<VIL<VIH<VOH<VS.L-MOSFET ModelRGSCGSRONOpen for vGS < VTClosed for vGS > VT{GSDvINRPU+_vOUTVSInverterTo N othergate inputs(1A) The static (CGS= 0) input-output characteristic of the inverter is as shown below.Determine the voltages VA, VBand VCthat define this characteristic. Express thevoltages in terms of VS, RPU, N and the L-MOSFET parameters.vOUTvINVSVSVAVBVC0VA:VB:VC:Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].(1B) In terms of the static discipline parameters (VOL, VIL, VIHand VOH), determine thevoltage range within which the threshold voltage VTmust be designed for the inverterto obey the static (CGS= 0) discipline at its input.≤ VT≤Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].(1C) Determine the resistance range within which the pull-up resistance RPUmust bedesigned for the inverter to obey the standard static (CGS= 0) discipline at itsoutput. Express the range in terms of VS, N, the L-MOSFET parameters and thestatic discipline parameters.≤ RPU≤Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].(1D) Assume that vIN(t) >VTfor t<0 so that the L-MOSFET switch is initially closed.For t ≥ 0, vINsteps to vIN(t) <VTso that the L-MOSFET switch opens. For thisinput, determine the dynamic (CGS> 0) response of the inverter. That is, determinevOUT(t) for t ≥ 0. Express vOUTin terms of VS, RPU, N, the L-MOSFET parameters.You may also use VA, VBand VCfrom Part 1A in your answer.vOUT(t ≥ 0):Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].Problem 2 – 30%This problem concerns the analysis of the MOSFET amplifier shown below. For the pur-poses of this analysis, assume that the MOSFET operates in its saturation region. Thecorresponding MOSFET characteristics are also given below.vINRD+_vOUTVSRSSaturation Region:vDS > vGS - VT > 0 iD = 0.5K ( vGS - VT )2(2A) Determine vOUTas a function of vIN.ExpressvOUTin terms of the circuit parametersand the MOSFET parameters.vOUT:Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].(2B) Let vIN= VIN+vinwhere VINand vinare the large-signal and small-signal componentsof vIN, respectively. Further, let vOUT= VOUT+voutwhere VOUTand voutare the large-signal and small-signal components of vOUT, respectively. Assume that the amplifieris biased with a value of VINthat results in saturated operation of the MOSFET.For this case, draw the circuit that models the small-signal behavior of the amplifier,and that can be used to determine voutfrom vin. Clearly label the components in themodel.Model:Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].(2C) Determine the small-signal gain vout/vinof the amplifier. Express the gain in termsof the amplifier parameters, the MOSFET parameters and the bias voltage VIN.vout/vin:Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].Problem 3 – 35%A signal generator having Thevenin resistance RSGis connected to Port #1 of a two-portnetwork as shown below. At t = 0, the Thevenin voltage vSG(t) of the signal generator takesa step from zero to VSG, and the voltage v2(t)ismeasuredatPort#2asshownbelowwiththe port op en-circuited. Note that α is a unitless constant satisfying 0 <α<1, and τ is atime constant. Assume that the Thevenin voltage of the signal generator is zero for a verylong time prior to the step.vSG(t)tVSG+_vSG(t)RSGSignal GeneratorNetworkPort#1Port#2+_v2(t)v2(t)t00αVSG( 1 - e-t/τ )αVSGVSG(3A) Which of the following could be the two-port network?RC#1 #2(A)RC#1#2(B)RC#1 #2(C)RC#1#2(D)RC#1 #2(E)Network (Circle One): A B C D
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