DOC PREVIEW
MIT 6 002 - Norton Equivalents and Logic Gates

This preview shows page 1-2 out of 5 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 5 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 5 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 5 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.002 – Electronic CircuitsFall 2005Lab 1: Thevenin/Norton Equivalents & Logic GatesHandout F05-018IntroductionThe first part of the lab explores the characterization of a network by its Thevenin and Nortonequivalents. The second part explores the static behavior of logic gates constructed with n-channelMOSFETs and resistors. You should complete the pre-lab exercises in your lab notebook beforecoming to lab. Then, carry out the in-lab exercises between September 26 and September 30.After completing the in-lab exercises, have a TA or LA check your work and sign your lab notebook.Finally, complete the post-lab exercises in your lab notebook, and turn in your lab notebook duringrecitation on Wednesday October 5.Pre-Lab ExercisesPre-Lab Exercises 1-1 and 1-2 explore the characterization of a network by its Thevenin and Nortonequivalents. Pre-Lab Exercises 1-3 through 1-5 explore the static behavior of logic gates.(1-1) Determine the Thevenin and Norton equivalents of the network shown in Figure 1 as viewedat its port.+-R3R2R1VFigure 1: Source-resistor network for Pre-Lab Exercises 1-1 and 1-2.(1-2) Evaluate the Thevenin and Norton equivalents of the network for the following values:V = 5 V; R1= 50 Ω; R2= 2.2 kΩ; R3= 1.5 kΩ.(1-3) Figure 2 shows a NOT gate, a NOR gate, and a NAND gate constructed from n-channelMOSFETs and 1 kΩ resistors. The figure also shows a switch-resistor model for the n-channel MOSFET. Using the switch-resistor model, compute vOUTfor all three gates. Indoing so, consider all combinations of input voltages; an input voltage may be either above orbelow the MOSFET threshold voltage VT. In each case, evaluate vOUTassuming RDS−ON=4 Ω. Summarize your results for each gate in a table.(1-4) Figure 3 shows a combinational logic circuit. Determine the input-output truth table forthis circuit.(1-5) Draw the circuit diagram for the combinational logic circuit shown in Figure 3 using thegates shown in Figure 2.1kΩ5VvOUTvIN+-+-1kΩ5VvOUT+vGS VTOpen:Closed:MOSFET ModelDSGRDS-ON5VvOUTvIN2+-vIN1+-NANDGate+-NOTGateNORGate1kΩvIN2vIN1+-+--vGSVT < >Figure 2: A NOT gate, a NOR gate, a NAND gate, and the switch-resistor MOSFET model.IN1IN2IN3OUTFigure 3: Combinational logic circuit for Pre-Lab Exercises 1-4 and 1-5.In-Lab ExercisesIn-Lab Exercises 1-1 through 1-3 explore the characterization of a network by its Thevenin andNorton equivalents. In-Lab exercises 1-4 through 1-9 explore the static behavior of logic gates.(1-1) Construct the network shown in Figure 4. However, before connecting the signal generatorto the remainder of the network, set its output voltage to a constant 5 V, and check thisoutput with the multi-meter. The network is the same as the one shown in Figure 1,with the function generator serving as both the voltage source and resistor R1. Note: Thefunction generator has two modes to compensate for the load impedance– 50 Ω and High Z.Make sure that your function generator is set to the High Z mode. Press [Shift] and then[Enter] to get to the menus. Using the dial, switch to menu D, the SYS MENU. Next pressthe down arrow twice. Use the dial to switch to HIGH Z. Then press [Enter] to save.+-50Ω 1.5kΩ2.2kΩv+-Signal GeneratoriFigure 4: Experimental source-resistor network.(1-2) Measure the open-circuit voltage and short-circuit current of the network with the multi-meter. Note that the multi-meter is itself a near open circuit when used as a voltmeter,and a near short circuit when used as an ammeter. Therefore, the direct connection ofthe multi-meter across the port implements the proper measurement in both cases. Yourresults from Pre-Lab Exercise 1-2 should show that both measurements are within the saferange for the multi-meter.(1-3) Connect a resistor across the network port and measure the port voltage v with the multi-meter. Do so for resistors having resistances of 560 Ω, 1 kΩ and 2.2 kΩ.(1-4) Construct the circuit shown in Figure 5, which is designed to measure the threshold voltageof the MOSFET; the MOSFET pin assignments are given in the attached data sheet. TheMOSFET should say 2N7000 on it. Make sure that you don’t accidentally reverse thepolarity of the MOSFET. The source should be connected to ground, and the drain to the1 kΩ resistor. (As evident from the MOSFET schematic in the datasheet, note that thedrain and soure terminals of discrete MOSFETs are not symmetric). Use the multi-meterto measure vGSand the oscilloscope to measure vDS, and set the signal generator to providea constant output. With vGSat 0 V, vDSshould be at 5 V. Gradually increase vGSuntilvDSstarts to fall. The value of vGSat which this occurs is VT.(1-5) Beginning with the circuit shown in Figure 5, remove the 1 kΩ resistor and the oscilloscopefrom the MOSFET drain. With vGSat 5 V, measure RDSwith the multi-meter. Thisresistance is RDS−ONfor vGS= 5 V; note that the multi-meter supplies a very small voltagewhen used as an ohmmeter.(1-6) Construct the NOT gate from Figure 2 and connect its input to a switch and 10 kΩ resistorV+-DSGSignal GeneratorTo MultimeterTo Oscilloscope50Ω1kΩ5VFigure 5: Circuit to measure VT.as shown in Figure 6. For both switch positions, that is for both logic input levels to thegate, measure vOUTwith the multi-meter.A switch pack and a 10 kΩ resistor array (10k SIP pn.A103J) have been chosen to simplifythe wiring of the switches to their associated resistors. Specifically, the switch pack can beplaced in the protoboard so that one side is on a common ground strip and each pin on theother side is on a separate trace. Then, the resistor array can be inserted into the protoboardalong side the switch pack so that separate resistors connect to each switch. Finally, thecommon pin of the resistor pack, designated by the white circle, can be connected to the 5V power supply through a single wire. A diagram of this setup is seen in Figure 7.(1-7) Construct the NOR gate from Figure 2. As for the NOT gate shown in Figure 6, connectthe inputs to the NOR gate to switches and 10 kΩ resistors. For all combinations of switchpositions, that is for all combinations of logic input levels to the gate, measure vOUTwiththe multi-meter. Save the NOR gate for In-Lab Exercise 1-9.(1-8) Repeat In-Lab Exercise 1-7 for the NAND gate. Save the NAND gate for In-Lab Exercise1-9.(1-9) Use the NOR gate and NAND gate to implement the combinational logic


View Full Document

MIT 6 002 - Norton Equivalents and Logic Gates

Documents in this Course
Quiz 2

Quiz 2

8 pages

Quiz 1

Quiz 1

14 pages

Quiz 1

Quiz 1

11 pages

Quiz 1

Quiz 1

10 pages

Quiz #2

Quiz #2

11 pages

Quiz 2

Quiz 2

16 pages

Quiz 2

Quiz 2

11 pages

Quiz #1

Quiz #1

26 pages

Quiz 1

Quiz 1

10 pages

Load more
Download Norton Equivalents and Logic Gates
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Norton Equivalents and Logic Gates and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Norton Equivalents and Logic Gates 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?