Name: 1MASSACHVSETTS INSTITVTE OF TECHNOLOGYDepartment of Electrical Engineeringand Computer Science6.002 – Electronic CircuitsDecemb er 19, 2001Final ExamNote: The pages in this exam are numbered 1-13. Please check that all pages are present.You may use three pages of notes and a calculator in this exam.Some of the questions in this exam are multiple choice. Some of the problems require you to circleall of the appropriate choices. We will look only at the circled choices: we will not consider longanswers for the multiple-choice questions.For long answers, please write clear and concise answers to the questions in the spaces provided inthis booklet. You may use extra paper, if needed, but the spaces we provide are surely big enoughto contain the simple answers we are looking for. You must be brief but complete and clear. Wewill certainly give you no credit for an answer that we cannot decode.You must put your name in the place provided at the top of each page of the exam. DO IT NOW!You must also put your name, the name of your tutor, and the name of your recitation instructorin the places provided below:Name:Tu t o r :Recitation Instructor:Problem Grade Grader12345ΣName: 21. Consider the CMOS logic circuit shown below. Assume that the ON resistance of each of thetransistors, both PMOS and NMOS transistors, is R. Also assume that we are only consideringvery low frequency or steady dc signals.AvOUTABBABBAC+4V(a) Assuming that only legitimate logic levels are applied to the inputs of this circuit, whichof the following voltages may be possible values of vOUT? Circle all answers that areappropriate.0 1 12/7 2 16/7 3 4(b) Which of the following input combinations cause large static power dissipation? Circleall answers that are appropriate.A=0B=0C=0A=1B=0C=0A=0B=1C=0A=1B=1C=0A=0B=0C=1A=1B=0C=1A=0B=1C=1A=1B=1C=1(c) It is proposed to eliminate the combinations that cause large static power dissipation bytying a single input to a high (1) or low (0) logic level. Circle all of the possibilities thatcould work, or the word “none” if no single assignment would work.A =0 B =0 C =0 A =1 B =1 C = 1 none(d) Assume that we connect the¯C input to the¯A input. In the space provided belowwrite a Boolean-logic expression for the value of vOUTin terms of A and B and theircomplements.Answer:Name: 32. Remember that two circuits are terminal equivalent if and only if they have identical behavior,as determined in terms of voltages between terminals and currents into terminals. For eachpair of circuits shown below, the circuits are terminal equivalent when the unspecified circuitparameters satisfy some relations. For each pair you are to determine the constraints on theparameters that make the circuits terminal equivalent.(a) In the space provided below write the relationship between C1and C2that makes thesecircuits equivalent.C1C2+−vi+−vi+−3vAnswer:(b) In the space provided below write the values of L and R that make these circuits terminalequivalent for sinusoidal excitations at the angular frequency of 500 radians/second.+-vi+-vi1 Fµ1kΩRL6HAnswer:Name: 4(c) In the space provided below write the values of vAand R in terms of vI, R1, R2,andR3that make these circuits terminal equivalent. You may assume that the opamp hasinfinite gain.+−viR2R3R3R1vI+−+−vivA+−R+−Answer:(d) In the space provided below write the constraints on L, R, V ,andI that make thesecircuits equivalent at a specified frequency ω.+−vi+−vivIiI1mH1kΩ+−ωiIωvI= I sin t= V cos tRLAnswer:Name: 53. The figure below shows a model for the output filter and load of a dc/dc power converter.The voltage source models the input from the power converter’s switching stage. The resistormodels the load of the power converter. The filter is composed of the inductor and thecapacitor. The parameters are L = 100 µHandC = 100 µF.INvOUTv+−+−LCR(a) Assume that the power converter has been operating with vIN(t)=5+5sin105t and aload of R =1Ωfor a long time. In the space provided below derive an expression forthe output voltage vOUT(t) using numerical element values.Answer:Name: 6(b) Now assume that the filter is supplied from a dc source, vIN(t) = 5. Assume that thesystem has been operating with a load of R = 1Ω for all t<0. At t = 0 the load changesto R =2Ω.i. The output voltage vOUT(t) has the form:vOUT(t)=V0+ V1e−αtcos ωt + V2e−αtsin ωt for t>0Determine α and ω.ii. Determine initial conditions for vOUT(0+)anddvOU Tdt0+.iii. Determine V0, V1and V2.Name: 74. We have learned that we can maximize the power dissipated in a load attached to a Th`eveninsource, as in the figure below, by arranging that the resistance of the load is equal to theresistance of the source.LRvO+−+−vTRTWe can define the power gain of such a network by the formulaG =v2O/RLv2T/(4RT)(a) In the space provided below give the numerical value of G for the circuit shown abovewhen RT= 100Ω and RL=1Ω.Answer:(b) In the space provided below show that G = 1 for a load matched to the source, and thatG<1 if the load is either too big or too small. (Remember, “The load is matched tothe source” means that we have chosen RLso that RL= RT.)Answer:Name: 8(c) It is proposed that if we insert a lossless network between the source and the load asshown below, we can improve the power gain, G.RTvORLRTRLLC= 1= 10H= 0.1FΩ= 100 Ω+−vTCL+−In the space provided below write the system function H(s)=VoVtfor this new network.Answer:Name: 9(d) The frequency response of the network of part 4c above, |H(jω)|, has the form shownbelow|H(jω)|ω0max |H||H(0)|In the spaces provided below give the values of the parameters requested.i. max |H| =max |H| is the height of the peak of the curve.ii. ω0=ω0is the angular frequency of the peak in the curve.iii. ∆ω =∆ω is the width of the curve where |H| =max|H|/√2.iv. H(0) =H(0) is the intercept of the curve on the ω =0axis.v. C =C is defined by |H(jω)|→C/ω2as ω →∞.Name: 10(e) Find the maximum power gain of this network, defined as the maximum value ofG =|Vo|2/RL|Vt|2/(4RT)as a function of frequency. Write your answer in the space provided below:Answer:Name: 115. The following circuit uses the small-signal characteristic of the diode to make an attenuatorcontrolled by the variable resistance R. In this problem we investigate how this might work.vI(t) O(t)vQ1Q2+−+15V+−1000CRDI1I2iDiGvSGvSDSourceDrain+−+−GatePMOS FETPMOS transistors have the same behavior as
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