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MIT 6 002 - Homework 11

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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.002 – Electronic Circuits Spring 2007 Homework #11 Handout S07-053 Issued 4/26/2007 - Due 5/11/2007 Introduction This homework assignment focu s es on the analysis and design of a system for playing back a digitally-stored audio signal. Additionally, this assignment serves as the pre-lab exercises for Lab #4, wh ich will involve the construction, testing and demonstration of the audio playback system. Consequently, you should save a copy of your results for use during Lab #4. A block diagram of the audio playback system is shown in Figure 1. At the center of the system is a digital memory in which 131,072 samples of the audio signal are stored. Each sample in the memory has a unique numerical address between 0 and 131,071, inclusive. Consecutive samples are stored at consecutive addresses. To obtain 131,072 consecutive samples of the audio signal, 16.384 seconds of continuous analog audio s ignal are first sampled at an 8-kHz rate. The analog audio samples are then digitized by an 8-bit analog-to-digital converter. That is, the samples are quantized to take on one of 256 possible discrete digital values between 0 and 255, inclusive. Here, the digital value of 0 corresponds to the most positive signal voltage, and the digital value of 255 corresponds to the most negative signal voltage. The resulting digital data is then written into the memory. To retrieve the stored aud io signal samples in sequence at the proper rate, the memory is addressed by a counter which counts from 0 to 131,071 at an 8-kHz rate established by an external clock. After counting to 131,071 the counter returns to 0, and the r etrieval process repeats itself. As the memory add ress increments, the corresponding data appears at the memory output. This data is converted back to an analog voltage in a piecewise constant mann er by a digital-to-analog converter. During the course of recording and playin g back the an alog audio signal, the signal is sampled Clock Counter D/A Converter Low-Pass Filter Volume ControlMemory Headphone Figure 1: Block diagram of the audio play back system. 1 Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].in time, quantized in amplitude, and reconstructed in a piecewise constant manner. As you will learn in 6.003, this p rocess introduces undesirable high-frequency components into the signal. To minimize the perceived impact of these components, the signal is filtered by a low-pass filter after it is reconstructed by the digital-to-analog converter. Finally, the s ignal is fed into a volume control stage which in turn drives a headphone. In the course of this homework assignment you will an alyze and design four of the functional blocks shown in Figure 1. These blocks are the clock, the digital-to-analog converter, the low-pass filter and the volume control. In Lab #4, you will construct these blocks and verify that they perform as desired. Then , you will combine them with the counter, the read-only memory and the speaker to construct and demonstrate the entire audio play-back system. Since you will construct the sys tem from the components in your 6.002 lab kit, your design of the blocks must account for the f act that the available components are limited. Problem 1: The Clock The circuit shown in Figure 2 is the system clock, which is a square-wave oscillator followed by a CMOS inverter; the inverter functions only as a buffer. The oscillator is constructed from another CMOS inverter, a resistor and a capacitor. Both inverters are powered between the positive supply voltage VS and ground, and both exhibit the hysteretic input-output characteristic defined in the figure. The inverters are otherwise ideal. (A) Assume that vCAP has jus t charged up to VH so that vOSC has jus t switched to 0 V. In terms of R, C, VL, and VH, how mu ch time elapses before vCAP decays to VL, which in turn causes vOSC to switch to VS? (B) Assume that vCAP has just decayed to VL so that that vOSC has just switched to VS. In terms of R, C, VL, VH, and VS, how much time elapses before vCAP charges up to VH, which in turn causes vOSC to switch to 0 V? (C) Determine the frequency of the oscillator in terms of R, C, VL, VH and VS. R C + vCLK vOSC + --IN OUT + vCAP vOUT-VS vIN VL VHVS Figure 2: The system clock. 2 Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].(D) Assume that VL = 1.8 V, VH = 3.0 V and VS = 5.0 V. Choose values for R and C so that the oscillator oscillates at or very near 8-kHz. Since oscillator frequency alone is not enough information to specify unique values for R and C, there is no single correct choice. Therefore, choose values for R and C that are easily implemented with the components in the 6.002 lab kit. (E) For the choice of R and C from Part (D), sketch and clearly label a single graph that displays vCAP, vOSC and vCLK as a function of time over one period of oscillation. Problem 2: The Digital-To-Analog Converter The circuit shown in Figure 3 is the digital-to-analog converter. The voltage sources vDB0 through vDB7 represent the voltages supplied by the eight data bits of the digital memory, DB0 through DB7. T hese voltages w ill be approximately 5 V when the corresponding data bit is a logical high, and approximately 0 V when the corresponding data bit is a logical low. The voltage vOFF, which is set by a potentiometer, is an offset voltage that is used to


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MIT 6 002 - Homework 11

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