Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.002 – Circuits & ElectronicsSpring 2005Problem Set #11Issued 4/20/05 – Due 5/4/05Int roductionThis homework assignment focuses on the analysis and design of a system for playing back adigitally-stored audio signal. Additionally, this assignment serves as the pre-lab exercises forLab #4, which will involve the construction, testing and demonstration of the audio playbacksystem. Consequently, you should save a copy of your results for use during Lab #4.A block diagram of the audio playback system is shown in Figure 1. At the center of the systemis a digital memory in which 32,768 samples of the audio signal are stored. Each sample in thememory has a unique numerical address between 0 and 32,767, inclusive. Consecutive samples arestored at consecutive addresses.To obtain 32,768 consecutive samples of the audio signal, 4.096 seconds of continuous analogaudio s ignal are first sampled at an 8-kHz rate. The analog audio samples are then digitized by an8-bit analog-to-digital converter. That is, the samples are quantized to take on one of 256 possiblediscrete digital values between 0 and 255, inclusive. Here, the digital value of 0 corresp on ds to themost positive audio s ignal level, and th e digital value of 255 corresponds to the most negative audiosignal level. The resulting digital data is then written into the memory.To retrieve the stored audio signal samp les in sequence at the proper rate, the memory isaddressed by a counter which counts from 0 to 32,767 at an 8-kHz rate established by an externalclock. After counting to 32,767 the counter returns to 0, and the retrieval process repeats itself.As the memory address increments, th e corresponding data appears at th e memory output. Thisdata is converted back to an analog voltage in a piecewise constant manner by a digital-to-analog(D/A) converter.During the course of recording and playing back the analog audio signal, the signal is sampledClockCounter D/AConverterLow-PassFilterPower AmpMemory SpeakerFigure 1: block diagram of the audio playback system.in time, qu antized in amplitude, and r econstructed in a piecewise constant m an ner. As you willlearn in 6.003, this pr ocess introduces undesirable high-frequency components into the signal. Tominimize the perceived impact of these components, the signal is filtered by a low-pass filter afterit is reconstructed by the digital-to-analog converter. Finally, the s ignal is amplified by a poweramplifier which in turn drives a speaker. In Lab #4, you will use a piezo-electric speaker, whichdoes not require much power. In this case, the final power-amplifier stage is not strictly necessary.Nonetheless, the stage is included here, and is used to implement volume control.In the cours e of this homework assignment you will analyze and design four of the fu nctionalblocks shown in Figure 1. These blocks are the clock, the digital-to-analog converter, the low-passfilter and the power amplifier. In Lab #4, you will construct these blocks and verify that theyperform as desired. Then, you will combine them with the counter, the read-only memory and thespeaker to construct and demonstrate the entire audio play-back system. Since you will constructthe system fr om the components in your 6.002 lab kit, your design of the b locks must account forthe fact that the available components are limited.Problem 1: The ClockThe circuit shown in Figure 2 is the system clock, which is a square-wave oscillator followed by aCMOS inverter; the inverter functions only as a (negative-gain) buffer. The oscillator is constructedfrom another CMOS inverter, a resistor and a capacitor. Both inverters are powered between thepositive supply voltage VSand ground, and both exhibit the hysteretic input-output characteristicdefined in the figure. The inverters are otherwise ideal.(A) Assume that vCAPhas just charged up to VHso th at vOSChas ju st switched to 0 V. How muchtime elapses before vCAPdecays to VL, which in turn causes vOSCto switch to VS?(B) Assume that vCAPhas just decayed to VLso th at that vOSChas just switched to VS. Howmuch time elapses before vCAPcharges up to VH, which in turn causes vOSCto switch to 0 V?(C) Determine the frequency of the oscillator in terms of R, C, VL, VHand VS.RC+vCLKvCAPvOSC+-+--INOUTvOUTvINVSVHVLVSFigure 2: the system clock.(D) Assume that VL= 1.8 V, VH= 3.0 V and VS= 5.0 V. Choose values for R and C so that theoscillator oscillates at or very near 8-kHz. Since oscillator frequency alone under specifies Rand C, there is no single correct choice. Therefore, choose values for R and C that are easilyimplemented with the components in the 6.002 lab kit.(E) For the choice of R and C from Part (D), sketch and clearly label a single graph that displaysvCAP, vOSCand vCLKas a function of time over one period of oscillation.Problem 2: The Digital-To-Analog ConverterThe circuit shown in Figure 3 is the d igital-to-analog converter. The voltage sources vDB0throughvDB7represent the voltages supplied by the eight data bits of the digital memory, DB0 thr oughDB7. These voltages will be approximately 5 V when the corresponding data bit is a logical high,and appr oximately 0 V when the corresponding data bit is a logical low. The voltage vOFF, whichis set by a potentiometer, is an offset voltage that is used to center the output of the converteraround 0 V. Assume that the op-amp in the converter is ideal.(A) Determine vDACas a function of vDB0through vDB7, and vOFF. Hint: use superposition.(B) With vOFF= 0 V, the output of the digital-to-analog converter should span the range of 0 Vto − 2.5 V. Thus, the output of the converter should be given byvDAC= −2.5 V7Xi=02i255DBiwhere each data bit DBi takes on the numerical value of 1 when high and 0 when low. In thismanner, each successive data bit from DB0 to DB7 is given a voltage weighting twice that ofthe preceding data bit, making it possible for the converter to output voltages from 0 V to−2.5 V in steps of −2.5/255 V. Given this, wh at must be the relationships between the valuesof R0through R7, and R8?The voltage rating of the piezo-electric speaker used in Lab #4 is approximately ±12.5 V.Since the low-pass filter and power amplifier between the converter and the speaker will bedesigned to provide a total gain of 10 over the frequency range of interest, the output range+--+vDAC+-vOFFR8R7vDB7+-R6vDB6+-R1vDB1+-R0vDB0+5V+-Figure 3: the
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