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MIT 6 002 - Problem Set #3

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Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.002 – Circuits & ElectronicsSpring 2004Problem Set #3Issued 2/18/04 – Due 2/27/04Exercise 3.1: A battery is measured to have an open-circuit voltage of 1.5 V. It can deliver2.5 A to a 0.5-Ω resistor. How much current can it deliver to a short circuit? Hint: consider theNorton equivalent of the battery.Exercise 3.2: This exercise applies two different analyses to determine the unknown nodevoltages in Network (A) shown below. It illustrates that the direct method of analysis is not alwaysthe simplest.(A) Using nodal analysis, find the unknown node voltages in Network (A). Hint: see Problem 1.3.(B) First, explain why Network (A) may be re-drawn as Network (B). Second, combine the left-hand source with the two left-most resistors to form their Thevenin equivalent, and redrawthe resulting network. Third, combine the right-hand source with the two right-most resistorsto form their Thevenin equivalent, and again redraw the resulting network. Finally, usingsuperposition, determine the two unknown node voltages in the thrice re-drawn version ofNetwork (A) thereby completing the analysis. Your answers to Parts (A) and (B) should bethe same.V3RR3RRRNetwork AVV3RR3RRRNetwork BExercise 3.3: A Norton equivalent network is used to excite a nonlinear resistor as shownbelow. The graphical i-v characteristic that defines the nonlinear resistor is also shown below.Determine the terminal current iNRand the terminal voltage vNRof the nonlinear resistor for allvalues of IN. Hint: consider using a load-line analysis to gain insight.INNonlinearResistor+_vNRiNRvNRiNRGNRVNRRNProblem 3.1: Consider the Boolean-logic buffer having the real input-output characteristicshown below. (The dashed diagonal is for referene.) The usual static discipline is to be defined forthis buffer such that VOL<VIL<VIH<VOH. The high-level noise margin for this static disciplineis VOH− VIH. The low-level noise margin for this static discipline is VIL− VOL.(A) If zero noise margin were acceptable, over what voltage range could VILbe chosen? What isthe corresponding voltage range of VOL?(B) What combination of VILand VOLmaximizes the low-level noise margin?(C) If zero noise margin were acceptable, over what voltage range could VIHbe chosen? What isthe corresponding voltage range of VOH?(D) What combination of VIHand VOHmaximizes the high-level noise margin?0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 100.10.20.30.40.50.60.70.80.91INPUT VOLTAGE [V]OUTPUT VOLTAGE [V]Problem 3.2: This problem shows that there is often more than one way in which to implementa particular Boolean logic function, and that the most direct way is not always the simplest. Here,the two-input exclusive-or (XOR) gate serves as an example. The Boolean logic function that thisgate implements is OUT = (IN1 ·IN2) + (IN1 · IN2). Thus, its output is true if one or the otherinput is true, but not both.(A) Using AND-gate, OR-gate and NOT-gate (inverter) Boolean logic symbols, implement a two-input XOR gate by directly implementing the Boolean logic function that defined it above.(B) Design an NMOS inverter, an NMOS two-input AND gate and an NMOS two-input OR gateusing a minimum of MOSFETs and pull-up resistors.(C) Combine your results from Parts (A) and (B) to implement an NMOS two-input XOR gate.Your implementation should require eleven MOSFETs and eight pull-up resistors.(D) Using truth tables, prove DeMorgan’s law. DeMorgan’s Law states thatA+B = A · B, orequivalently that A + B =A · B, or equivalently that A · B=A+B, or equivalently, thatA · B=A+B. (Note that the second version of DeMorgan’s Law can be derived by invertingthe first version, and that the third and fourth versions can be derived from the second andfirst versions, respectively, by substitutingAforAandBforB.(E) Using only inverters and two-input NOR gates, implement an alternative NMOS two-inputXOR gate. This can be done with as few as nine MOSFETs and six pull-up resistors. Hint:use DeMorgan’s Law to modify your result found in Part (A).Problem 3.3: Consider the NMOS two-input OR gate shown below. This gate is to beimplemented with MOSFETs having 1 V ≤ VT≤ 4Vand103Ω ≤ RON≤ 106Ω, and pull-upresistors having 103Ω ≤ RPU≤ 106Ω. (The inequalities express a permissible design space asopposed to a range of manufacturing uncertainty.) The MOSFETs and pull-up resistors need nothave identical parameters.Complete the design of the OR gate by choosing values for each VT, RONand RPUso that: VOL=1V; VIL=2V;VIH=3V;VOH= 4 V; and the power dissipated by the gate is minimized. If anyparameter does not have a unique design value, then give the permissible range for that parameter.Assume VS=5V.VIN1VIN2M1M2M3RPU1RPU2VS+_VOUTProblem 3.4: The switch-resistor (SR) model of a MOSFET is a highly simplified modelthat is nonetheless very useful for describing the behavior of a MOSFET in a digital logic circuit.However, this model is so simplified that it can lead to inconsistent analyses in some cases, asillustrated by this problem.Consider the analysis of the two-input NAND and two-input NOR gates shown below. Assume thatall MOSFETS in these gates behave according to the SR model with a threshold voltage VT=1V,and on-state resistance RON. Further, let RPU= RON,andVS=3V.(A) Consider the two-input NAND gate. Let VIN1= VIN2=1.5 V. Assume that M2 is on anddetermine vOUTand vGSfor M2. (Is M1 on or off?) Is the value of vGSconsistent with theassumption that M2 is on?(B) Again consider the two-input NAND gate, and again let VIN1= VIN2=1.5 V. Now assumethat M2 is off and determine vOUTand vGSfor M2. Is the value of vGSconsistent with theassumption that M2 is off?(C) From your answers to Parts (A) and (B) you should conclude that M2 can be neither on noroff. What characteristics of the SR model and the design of the two-input NAND gate allowthis inconsistency to occur? How do you think the real circuit actually behaves?(D) How high must VIHbe defined for the two-input NAND gate so that the inconsistent analysisfound above is inconsequential to the proper operation of the gate?(E) Consider now the two-input NOR gate. Can its analysis produce the same inconsistency forany combination of parameter values? Why or why


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MIT 6 002 - Problem Set #3

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