Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.002 – Circuits & ElectronicsSpring 2005Lab #1: Thevenin/Norton Equivalents & Logic GatesIntroductionThis lab has two independent parts, each with pre-lab, in-lab and post-lab exercises. The first partexplores the characterization of a network by its Thevenin and Norton equivalents. The second partexplores the static behavior of logic gates constructed with n-channel MOSFETs and resistors. Youshould complete the pre-lab exercises in your lab notebook before coming to lab. Then, carry outthe in-lab exercises on your assigned lab day between February 28 and March 4. After completingthe in-lab exercises, have a TA or LA check your work and sign your lab notebook. Finally, completethe post-lab exercises in your lab notebook, and turn in your lab notebook during recitation onWednesday March 9.Pre-Lab ExercisesPre-Lab Exercises 1-1 and 1-2 explore the characterization of a network by its Thevenin and Nortonequivalents. Pr e-Lab Exercises 1-3 through 1-5 explore the static behavior of logic gates.(1-1) Determine the Thevenin and Norton equivalents of the network show n in Figure 1 as viewedat its port.(1-2) Evaluate the Thevenin and Norton equivalents of the network for the following values:V = 5 V; R1= 50 Ω; R2= 2.2 kΩ; R3= 1.5 kΩ.(1-3) Figure 2 shows a NOT gate, or inverter, a NOR gate and a NAND gate constructed fromn-channel MOSFETs and 1 kΩ resistors. The figure also show s a switch-resistor model forthe n-channel MOSFET. Using the switch-resistor model, compute vOUTfor all three gates.In doing so, consider all combinations of input voltages; an input voltage may be eitherabove or below the MOSFET threshold voltage vT. In each case, evaluate vOUTassumingRDS−ON= 4 Ω. Summarize your results for each gate in a table.(1-4) Figure 3 shows a combinational logic circuit. Determine the input-output truth table forthis circuit.(1-5) Draw the circuit diagram for th e combinational logic circuit shown in Figure 3 using the+-R3R2R1VFigure 1: source-resistor network for Pre-Lab Ex ercises 1-1 and 1-2.gates shown in Figure 2.In-Lab ExercisesIn-Lab Exercises 1-1 through 1-3 explore the characterization of a network by its Thevenin andNorton equivalents. In-Lab exercises 1-4 through 1-9 explore the static behavior of logic gates.(1-1) Construct the network shown in Figure 4. However, before connecting the signal generatorto the remainder of the network, set its output voltage to a constant 5 V, and check thisoutput with the multi-meter. Note that the network is the same as that shown in Figure 1,with the function generator serving as both the voltage source and resistor R1. Note thatthe function generator has two modes for displaying voltage: 50 Ω and High Z. Make surethat your function generator is set to the High Z mode. Press [Shift] and then [Enter] toget to the menus. Using the dial, switch to menu D, the SYS MENU. Next press the downarrow twice. Use the dial to switch to HIGH Z. Then press [Enter] to save.(1-2) Measure the open-circuit voltage and short-circuit current of the network with the multi-meter. Note that the multi-meter is itself a near open circuit when used as a voltmeter,and a near short circuit when used as an ammeter. Therefore, the direct connection ofthe multi-meter across the port implements the proper measurement in both cases. Yourresults from P re-Lab Exercise 1-2 should show that both measurements are within the saferange for the multi-meter.(1-3) Connect a resistor across the port of the network and measure the port voltage v with themulti-meter. Do so for resistors having resistances of 560 Ω, 1 kΩ and 2.2 kΩ.1kΩ5VVOUTVIN+-+-1kΩ5VVIN2VIN1+-+-VOUT+-VGSVT≤Open:Closed:VGSVT>MOSFET ModelDSGRDS-ON5VVOUTVIN2+-VIN1+-NANDGate+-NOTGateNORGate1kΩFigure 2: a NOT gate, a NOR gate, a NAN gate, and th e sw itch-resistor MOSFET model.IN1IN2IN3OUTFigure 3: combinational logic circuit for Pre-Lab Exercises 1-4 and 1-5.(1-4) Construct the circuit shown in Figure 5 to measure the threshold voltage of the MOSFET.The MOSFET should be labeled “2N7000”, an d its pin assignments are given in the attacheddata sheet. Use the multi-meter to measure vGSand the oscilloscop e to measure vDS, andset the signal generator to provide a constant output. With vGSat 0 V, vDSshould be at 5V. Gradually increase vGSuntil vDSstarts to fall. The value of vGSat which this occurs isvT. Caution: avoid handling the MOSFET by its leads because it can be damaged by staticelectricity. Also, be careful not to reverse the MOSFET leads when constructing the circuit.(1-5) Beginning with the circuit shown in Figure 5, disconnect the 1 kΩ resistor and the oscil-loscope from the MOSFET drain. With vGSat 5 V, measure RDSwith the multi-meter.This resistance is RDS−ONfor vGS= 5 V; note that the mu lti-meter supplies a very smallvoltage when used as an ohmmeter.(1-6) Construct the NOT gate from Figure 2 and connect its inp ut to a switch and 10 kΩ resistoras shown in Figure 6. For both switch positions, that is for both logic input levels to thegate, measure vOUTwith the multi-meter.The switch pack and the 10 kΩ resistor array have been chosen to simplify the wiring ofthe switches to their associated resistors. Specifically, the switch pack can be placed in theprotoboard so that one side is on a common ground strip and each p in on the other sideis on a separate trace. Then, the resistor pack can be inserted into the protoboard alongside the switch pack so that separate resistors connect to each switch. Finally, the commonpin of the resistor pack can be connected to the 5 V power supply through a single wire.Caution: the switch-pack pins are fragile, and they can also pop out of the protoboard.(1-7) Construct the NOR gate from Figure 2. As for the NOT gate shown in Figure 6, connect+-50Ω 1.5kΩ2.2kΩv+-Signal GeneratoriFigure 4: experimental source-resistor network.V+-DSGSignal GeneratorTo MultimeterTo Oscilloscope50Ω1kΩ5VFigure 5: circuit to measure vT.the inputs to the NOR gate to switch es and 10 kΩ resistors. For all combinations of switchpositions, th at is for all comb inations of logic input levels to the gate, measure vOUTwiththe multi-meter. Save the NOR gate for In-Lab Exercise 1-9.(1-8) Repeat In-Lab Exercise 1-7 for th e NAND gate. Save the NAND gate for In-Lab Exercise1-9.(1-9) Use the NOR gate and NAND gate to implement the combinational logic circuit of Figure3, as
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