1Week 2 Status UpdateCSE 141L - Oct. 10, 2008Announcements Lab 2, Part 1 is up Due Friday, Oct 17 at NOON Sign up for the RSS feed to stay up-to-date with announce. Common question: “What percentage of grade is lab1 worth?” Evasive answer: Not a lot but… don’t fall behind now! Lab partner search Lab 2 is individual but you should aim to find a partner bynext Friday (Oct. 17) E-mail sat with your partner and TEAM NAME2Responses to Xilinx “Why doesn’t this work?” “It can’t be this bad. Maybe I just need toreinstall!” “I hate you, Xilinx!” “Isn’t there an open-source alternative?” “I’m never going to get this to work” “OK, maybe I should just restart the project.” “It worked (somehow). I can handle this…”Lab 2: Build your fetch Unit Overview: Part A: Design the datapath for fetch unit We give you a datapath schematic Leaf modules in RTL style, datapath uses structuralstyle Part B: Implement fetch unit control and testfunctionality3Fetch Unit OverviewI-MemFIFOfetchinstructiondequeueFIFOFIFOFIFOFIFOFIFOFIFOFIFOFIFOFIFOFIFOExec UnitFetch UnitRole of Fetch Unit Supply instructions to execution unit How to handle branches? Don’t wait… predict! (p-bit) What if we are wrong? Service Inst-Mem operations Load/Store instructionsP Free Bits Offset4Fetch Unit InterfaceFetch UnitInstruction(data, addr, valid)dequeuerestartrestart_addrmemory req (load, store, addr, store_data)load_data, load_validExec Unit8Advanced HardwareDesign with VerilogBy Sat Garcia59Complete the quote “Good artists __________ .Great artists __________.”- Pablo Picasso The following slides are only slightly modifiedfrom those in the MIT 6.375 course http://csg.csail.mit.edu/6.375/copysteal10Designing a GCD Calculator Euclid’s Algorithm for GCD (in C):int GCD( int inA, int inB){ int done = 0; int A = inA; int B = inB; while ( !done ) { if ( A < B ) // if A < B, swap values { swap = A; A = B; B = swap; } else if ( B != 0 ) // subtract as long as B isn’t 0 A = A - B; else done = 1; } return A;}How do we implementthis in hardware?Adapted from Arvind and Asanovic's MIT 6.375 lecture611Take 1: Behavioral Verilogmodule gcdGCDUnit_behav#( parameter W = 16 ) // parameterize for better reuse( input [W-1:0] inA, inB, output [W-1:0] out); reg [W-1:0] A, B, out, swap; integer done; always @(*) begin done = 0; A = inA; B = inB; while ( !done ) begin if ( A < B ) swap = A; A = B; B = swap; else if ( B != 0 ) A = A - B; else done = 1; end out = A; endendmoduleWhat’s wrong with this approach?Doesn’t synthesize! (notice thatdata dependent loop?)Adapted from Arvind and Asanovic's MIT 6.375 lecture12Making the code synthesizable Start with behavioral and find out whathardware constructs you’ll need Registers (for state) Functional units Adders / Subtractors Comparators ALU’s713Identify the HW structuresmodule gcdGCDUnit_behav#( parameter W = 16 )( input [W-1:0] inA, inB, output [W-1:0] out); reg [W-1:0] A, B, out, swap; integer done; always @(*) begin done = 0; A = inA; B = inB; while ( !done ) begin if ( A < B ) swap = A; A = B; B = swap; else if ( B != 0 ) A = A - B; else done = 1; end out = A; endendmoduleState → RegistersLess than comparatorEquality ComparatorSubtractorAdapted from Arvind and Asanovic's MIT 6.375 lecture14Next step: define module portsinput_availableoperands_bits_Aoperands_bits_Bresult_bits_dataresult_takenresult_rdyclk resetAdapted from Arvind and Asanovic's MIT 6.375 lecture815Implementing the modules Two step process:1. Define datapath2. Define control/control pathControlDatapathData inputsData outputControl in/outputsControl in/outputsAdapted from Arvind and Asanovic's MIT 6.375 lecture16Developing the datapathBA = inA; B = inB;while ( !done )begin if ( A < B ) swap = A; A = B; B = swap; else if ( B != 0 ) A = A - B; else done = 1;endY = A;zero? ltAsubAlso need a couple MUXsAdapted from Arvind and Asanovic's MIT 6.375 lecture917Adding controlBAmuxselAregenBmuxselBregenA < BB = 0zero? ltAsubA = inA; B = inB;while ( !done )begin if ( A < B ) swap = A; A = B; B = swap; else if ( B != 0 ) A = A - B; else done = 1;endY = A;Adapted from Arvind and Asanovic's MIT 6.375 lecture18Datapath modulemodule gcdDatapath#( parameter W = 16 )( input clk, // Data signals input [W-1:0] operands_bits_A, input [W-1:0] operands_bits_B, output [W-1:0] result_bits_data, // Control signals (ctrl->dpath) input A_en, input B_en, input [1:0] A_mux_sel, input B_mux_sel, // Control signals (dpath->ctrl) output B_zero, output A_lt_B);BAselAenBselBenA < BB = 0zero? ltAsubAdapted from Arvind and Asanovic's MIT 6.375 lecture1019Implementing datapath modulewire [W-1:0] B;wire [W-1:0] sub_out;wire [W-1:0] A_mux_out;3inMUX#(W) A_mux( .in0 (operands_bits_A), .in1 (B), .in2 (sub_out), .sel (A_mux_sel), .out (A_mux_out));wire [W-1:0] A;ED_FF#(W) A_ff // D flip flop( // with enable .clk (clk), .en_p (A_en), .d_p (A_mux_out), .q_np (A));wire [W-1:0] B_mux_out;2inMUX#(W) B_mux( .in0 (operands_bits_B), .in1 (A), .sel (B_mux_sel), .out (B_mux_out));ED_FF#(W) B_ff( .clk (clk), .en_p (B_en), .d_p (B_mux_out), .q_np (B));2inEQ#(W) B_EQ_0 (.in0(B),in1(W'd0),.out(B_zero) );LessThan#(W) lt ( .in0(A),.in0(B),.out(A_lt_B) );Subtractor#(W) sub(.in0(A),in1(B),.out(sub_out) );assign result_bits_data = A;Remember:Functionality only in“leaf” modules!Adapted from Arvind and Asanovic's MIT 6.375 lecture20State machine for controlWAITCALCDONEinput_availble( B = 0 )result_takenWait for new inputsSwapping and subtractingWait for result to be grabbedresetAdapted from Arvind and Asanovic's MIT 6.375 lecture1121Implementing control moduleBAselAenBselBenA < BB = 0zero? ltAsubmodule gcdControlUnit( input clk, input reset, // Data signals input input_available, input result_rdy, output result_taken, // Control signals (ctrl->dpath) output A_en, output B_en, output [1:0] A_mux_sel, output B_mux_sel, // Control signals (dpath->ctrl) input B_zero, input A_lt_B);Remember: Keep nextstate (combin.), stateupdate (seq.), andoutput logic separated!Adapted from Arvind and Asanovic's MIT 6.375 lecture22State update logic Remember: keep state