Week 2 Status Update CSE 141L Oct 10 2008 Announcements Lab 2 Part 1 is up Common question What percentage of grade is lab 1 worth Due Friday Oct 17 at NOON Sign up for the RSS feed to stay up to date with announce Evasive answer Not a lot but don t fall behind now Lab partner search Lab 2 is individual but you should aim to find a partner by next Friday Oct 17 E mail sat with your partner and TEAM NAME 1 Responses to Xilinx Why doesn t this work It can t be this bad Maybe I just need to reinstall I hate you Xilinx Isn t there an open source alternative I m never going to get this to work OK maybe I should just restart the project It worked somehow I can handle this Lab 2 Build your fetch Unit Overview Part A Design the datapath for fetch unit We give you a datapath schematic Leaf modules in RTL style datapath uses structural style Part B Implement fetch unit control and test functionality 2 Fetch Unit Overview I Mem fetch FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO dequeue Exec Unit instruction Fetch Unit Role of Fetch Unit Supply instructions to execution unit How to handle branches Don t wait predict p bit P Free Bits Offset What if we are wrong Service Inst Mem operations Load Store instructions 3 Fetch Unit Interface dequeue Instruction data addr valid restart restart addr Fetch Unit Exec Unit memory req load store addr store data load data load valid Advanced Hardware Design with Verilog By Sat Garcia 8 4 Complete the quote copy Good artists steal Great artists Pablo Picasso The following slides are only slightly modified from those in the MIT 6 375 course http csg csail mit edu 6 375 9 Designing a GCD Calculator Euclid s Algorithm for GCD in C int GCD int inA int inB int done 0 int A inA int B inB while done if A B if A B swap values swap A A B B swap else if B 0 subtract as long as B isn t 0 A A B else done 1 return A Adapted from Arvind and Asanovic s MIT 6 375 lecture How do we implement this in hardware 10 5 Take 1 Behavioral Verilog module gcdGCDUnit behav parameter W 16 parameterize for better reuse input W 1 0 inA inB output W 1 0 out reg W 1 0 A B out swap integer done always begin done 0 A inA B inB while done begin if A B swap A A B B swap else if B 0 A A B else done 1 end What s wrong with this approach Doesn t synthesize notice that data dependent loop out A end endmodule 11 Adapted from Arvind and Asanovic s MIT 6 375 lecture Making the code synthesizable Start with behavioral and find out what hardware constructs you ll need Registers for state Functional units Adders Subtractors Comparators ALU s 12 6 Identify the HW structures module gcdGCDUnit behav parameter W 16 input W 1 0 inA inB output W 1 0 out reg W 1 0 A B out swap integer done always begin done 0 A inA B inB while done begin if A B swap A A B B swap else if B 0 A A B else done 1 end State Registers Less than comparator Equality Comparator Subtractor out A end endmodule 13 Adapted from Arvind and Asanovic s MIT 6 375 lecture Next step define module ports input available result rdy result taken operands bits A result bits data operands bits B clk reset 14 Adapted from Arvind and Asanovic s MIT 6 375 lecture 7 Implementing the modules Two step process 1 Define datapath 2 Define control control path Control in outputs Control Control in outputs Data output Data inputs Datapath 15 Adapted from Arvind and Asanovic s MIT 6 375 lecture Developing the datapath Also need a couple MUXs zero lt A inA B inB A sub B while done begin if A B swap A A B B swap else if B 0 A A B else done 1 end Y A 16 Adapted from Arvind and Asanovic s MIT 6 375 lecture 8 Adding control A mux sel A re g en B mux sel B re g en B 0 A B zero lt A inA B inB A while done begin if A B swap A A B B swap else if B 0 A A B else done 1 end sub B Y A 17 Adapted from Arvind and Asanovic s MIT 6 375 lecture Datapath module module gcdDatapath parameter W 16 input clk Data signals input W 1 0 operands bits A input W 1 0 operands bits B output W 1 0 result bits data Control signals ctrl dpath input A en input B en input 1 0 A mux sel input B mux sel A A sel en B B sel en A B 0 A B zero lt sub B Control signals dpath ctrl output B zero output A lt B 18 Adapted from Arvind and Asanovic s MIT 6 375 lecture 9 Implementing datapath module wire W 1 0 B wire W 1 0 sub out wire W 1 0 A mux out wire W 1 0 B mux out 2inMUX W B mux in0 operands bits B in1 A sel B mux sel out B mux out Remember ED FF W B ff Functionality only clk clk leaf modules en p B en d p B mux out q np B 3inMUX W A mux in0 operands bits A in1 B in2 sub out sel A mux sel out A mux out wire W 1 0 A ED FF W A ff D flip flop with enable clk clk en p A en d p A mux out q np A 2inEQ W B EQ 0 in0 B in1 W d0 out B zero LessThan W lt in0 A in0 B out A lt B Subtractor W sub in0 A in1 B out sub out assign result bits data A in 19 Adapted from Arvind and Asanovic s MIT 6 375 lecture State machine for control reset WAIT Wait for new inputs input availble CALC Swapping and subtracting B 0 result taken DONE Wait for result to be grabbed 20 Adapted from Arvind and Asanovic s MIT 6 375 lecture 10 Implementing control module module gcdControlUnit input input A A sel en clk reset Data signals input input available input result rdy output result taken Control signals ctrl dpath output A en output B en output 1 0 A mux sel output B mux sel Control signals dpath ctrl input B zero input A lt B B B sel en B 0 A B zero lt A sub B Remember Keep next state combin state update seq and output logic separated 21 Adapted from Arvind and Asanovic s MIT 6 375 lecture State update logic Remember keep state update next state calculation and output logic separated localparam WAIT 2 d0 …