Datapath Design Coding Standards and Lab 2 1 Separating Control From Data datapath is where data moves from place to The place Computation happens in the datapath No decisions are made here Things you should find in a datapath Muxes Registers ALUs Wide busses 34 bits for data 17 bits for instructions These components are physically large In a real machine their spatial relationship are important Mostly about wiring things up 2 Separating Control From Data is where decisions are made Control Things you will there State machines Random lots of complex logic Little state maybe just a single register Spatial relationships are harder to reason about or exploit they are qualitatively so different we will Because use different coding styles for each These are best practices from people who build real chips Following them will save you lots of pain If you don t follow them and you have problem the TAs and I will tell you to go fix the coding style issues first 3 Basic Design reset Control inputs control outputs clk Control Outputs Data inputs Signals controlling the datapath Signals providing information to control Datapath clk reset 4 Separating Design from Implementation you will learn debugging hardware is slow As first Design Draw your schematic in complete detail names and everything Signal the state machine for your control Design Write out the truth tables for your control signals TheOurimplement coding standards are recipe for implementing datapath and control Verilog is really just about translating your design Writing into Verilog It should be almost completely mechanical 5 Designing the Datapath datapaths is easier than it may seem Designing Design You start with a specification of the algorithm your circuit should implement Figure out what operations need to be performed on the data and how data will flow between operations Draw the schematic Remember the datapath does not make decisions It generates data needed to make the decisions It provides the flexibility implement decisions that the control might make Implement Instantiate those components and connect them with wires Test 6 Example Greatest Common Devisor second set of slides from Arvind See code in the slides is buggy The source code for a correct implementation is The available on the course web site 7 Lab 2 Datapath for a simple processor simple design but includes all the parts you Very will need later Memories Registers ALUs Wires Our IO interface Datapath and control 8 The Architecture size 8 bits Word address Data memory contains 256 bytes length 16 bits Instruction Instruction memory contains 8192 instruction words instructions two argument instructions Nine Math Add Sub Mult r1 r1 op r2 Memory LD ST Constants LI IO Read Write Control Halt registers Four format Instruction 4 bit opcode dst src2 immediate 8 bits 9 Basic Algorithm byte inst byte int reg 4 imem 8192 mem 256 PC While halted inst imem PC Get the instructions opcode ExtractOPcode inst decode it r1 ExtractR1 inst r2 ExtractR2 inst imm ExtractImm inst collect the inputs and perform the op byte r DoOp opcode reg r1 reg r2 write the results if opcode needs to write a result reg r1 r What s next PC 10 Basic Algorithm byte DoOp Opcode op byte r1 byte r2 byte imm switch op case ADD return r1 r2 case SUB return r1 r2 case LD return mem r2 case ST return mem r2 r1 Why not mem r1 r2 case Read out port r1 wait for data to be taken case Write wait for value to appear on in port return in port case Halt halted true 11