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UCSD CSE 141L - ISE 11.5 Quick Start Tutorial

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ISE 11.5 Quick Start Tutorial (Created for CSE 141L) (Derived from Xilinx ‘ISE 10.1 Quick Start Tutorial’ and Digilent ‘Xilinx® ISE Simulator (ISim) with Verilog Test Fixture Tutorial’)Starting the ISE Software To start ISE, double-click the desktop icon, or start ISE from the Start menu by selecting: Start → All Programs → Xilinx ISE Design Suite 11 ->ISE→ Project Navigator Note: Your start-up path is set during the installation process and may differ from the one above. Create a New Project Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board. To create a new project: 1. Select File > New Project... The New Project Wizard appears. 2. Type tutorial in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. 6. Fill in the properties in the table as shown below: ♦ Product Category: All ♦ Family: Spartan3 ♦ Device: XC3S200 ♦ Package: FT256 ♦ Speed Grade: -4 ♦ Top-Level Source Type: HDL ♦ Synthesis Tool: XST (VHDL/Verilog) ♦ Simulator: ISE Simulator (VHDL/Verilog) ♦ Preferred Language: Verilog ♦ Verify that Enable Enhanced Design Summary is selected. Leave the default values in the remaining fields. When the table is complete, your project properties will look like the following:Figure 2: Project Device Properties 7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete. Create an HDL Source In this section, you will create the top-level HDL file for your design. Creating a Verilog Source Create the top-level Verilog source file for the project as follows: 1. Click New Source in the New Project dialog box. 2. Select Verilog Module as the source type in the New Source dialog box. 3. Type in the file name counter. 4. Verify that the Add to Project checkbox is selected. 5. Click Next. 6. Declare the ports for the counter design by filling in the port information as shown below: Figure 5: DefineModule 7. Click Next, then Finish in the New Source Information dialog box to complete the new source file template. 8. Click Next, then Next, then Finish. The source file containing the counter module displays in the Workspace, and the counter displays in the Sources tab, as shown below: Figure 6: New Project in ISE Using Language Templates (Verilog) The next step in creating the new source is to add the behavioral description for counter. Use a simple counter code example from the ISE Language Templates and customize it for the counter design. 1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement. 2. Open the Language Templates by selecting Edit → Language Templates… Note: You can tile the Language Templates and the counter file by selecting Window → Tile Vertically to make them both visible. 3. Using the “+” symbol, browse to the following code example: Verilog → Synthesis Constructs → Coding Examples → Counters → Binary →Up/Down Counters → Simple Counter 4. With Simple Counter selected, select Right Click → Use in File, File toolbar button. This step copies the template into the counter source file. 5. Close the Language Templates. Final Editing of the Verilog Source 1. To declare and initialize the register that stores the counter value, modify the declaration statement in the first line of the template as follows: replace: reg [<upper>:0] <reg_name>; with: reg [3:0] count_int = 0; 2. Customize the template for the counter design by replacing the port and signal name placeholders with the actual ones as follows: ♦ replace all occurrences of <clock> with CLOCK ♦ replace all occurrences of <up_down> with DIRECTION ♦ replace all occurrences of <reg_name> with count_int 3. Add the following line just above the endmodule statement to assign the register value to the output port: assign COUNT_OUT = count_int; 4. Save the file by selecting File → Save. When you are finished, the code for the counter will look like the following: module counter(CLOCK, DIRECTION, COUNT_OUT); input CLOCK; input DIRECTION; output [3:0] COUNT_OUT; ); reg [3:0] count_int = 0; always @(posedge CLOCK) if (DIRECTION) count_int <= count_int + 1; else count_int <= count_int - 1; assign COUNT_OUT = count_int; endmodule You have now created the Verilog source for the tutorial project. Checking the Syntax of the New Counter Module When the source files are complete, check the syntax of the design to find errors and typos. 1. Verify that Implementation is selected from the radio buttons in the Sources window. 2. Select the counter design source in the Sources window to display the related processes in the Processes window. 3. Click the “+” next to the Synthesize-XST process to expand the process group. 4. Double-click the Check Syntax process. Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able tosimulate or synthesize your design. 5. Close the HDL file. Design Simulation Verifying Functionality using Behavioral Simulation Once the syntax is checked add a Verilog Test Fixture file to the project to run simulation. 1. Right click on the devices in the sources window and select New Source… 2. In the New Source Wizard select Verilog Test Fixture for the source type and enter and meaningful name for the file. 3. After clicking Next, the following dialog box asks you to select the source file you want to associate with the given test fixture file. This dictates which source file you actually run the simulation on. In this tutorial, we run the simulation on the top-level module of the design (counter.v). Click Next and finish to complete the creation 4. Select Simulation in the sources window to view the file. 5. Double click on the newly created testbench file. You will see that Xilinx has already generated lines of code to start the input definition. The code includes a. A comment block template for documentation b. A module statement c. A UUT Instantiation d. Input Instantiation Scroll down


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UCSD CSE 141L - ISE 11.5 Quick Start Tutorial

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